llvm-svn: 74345

nesting order of nested AddRec expressions to skip the transformation
if it would introduce an AddRec with operands not loop-invariant
with respect to its loop.

llvm-svn: 74343

instead of skipping).

llvm-svn: 74341

llvm-svn: 74340

are loop invariant, not just the start operand.

llvm-svn: 74338

llvm-svn: 74337

Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.

llvm-svn: 74336

llvm-svn: 74334

llvm-svn: 74333

llvm-svn: 74332

llvm-svn: 74330

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

llvm-svn: 74328

llvm-svn: 74327

llvm-svn: 74326

the SelectionDAG::getGlobalAddress function properly looks through
aliases to determine thread-localness, but then passes the GV* down
to GlobalAddressSDNode::GlobalAddressSDNode which does not.  Instead
of passing down isTarget, just pass down the predetermined node
opcode.  This fixes some assertions with out of tree changes I'm 
working on.

llvm-svn: 74325

llvm-svn: 74322

llvm-svn: 74321

llvm-svn: 74320

we had multiple type planes and these lookups were expensive.

llvm-svn: 74319

llvm-svn: 74317

llvm-svn: 74316

llvm-svn: 74315

llvm-svn: 74313

SDNode::print_details to eliminate a ton of near-duplicate code.

llvm-svn: 74311

llvm-svn: 74310

llvm-svn: 74306

used by both the user-visible intrinsics defined by ARM and the
corresponding GCC builtins.

llvm-svn: 74300

llvm-svn: 74298

llvm-svn: 74295

llvm-svn: 74294

llvm-svn: 74293

llvm-svn: 74291

llvm-svn: 74289

Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288

llvm-svn: 74285

llvm-svn: 74284

Patch by Xerxes Ranby.

llvm-svn: 74283

llvm-svn: 74282

llvm-svn: 74281