MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

predessors of exit blocks from tail merging
consideration.

llvm-svn: 52985

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

llvm-svn: 52495

elements that have been erased.  Based on a patch
by Nicolas Capens.

llvm-svn: 51485

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

if those blocks consist entirely of common instructions;
merging will not add an extra branch in this case.

llvm-svn: 51006

semantically identical, but little difference in
either results or execution speed; but it's much
easier to read, at least IMO.

llvm-svn: 50999

no functional change.

llvm-svn: 50921

case where there are multiple blocks with a large
number of common tail instructions more efficiently
(compile time optimization).

llvm-svn: 50916

llvm-svn: 50696

Teach branch folding pass about implicit_def instructions. Unfortunately we can't just eliminate them since register scavenger expects every register use to be defined. However, we can delete them when there are no intra-block uses.  Carefully removing some implicit def's which enable more blocks to be optimized away.

llvm-svn: 49461

llvm-svn: 47703

PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB.

llvm-svn: 47301

llvm-svn: 46930

llvm-svn: 46514

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674

llvm-svn: 45667

llvm-svn: 45656

e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464

llvm-svn: 45418

Improve branch folding by recgonizing that explict successor relationships impact the value of fall-through choices.

llvm-svn: 44785

llvm-svn: 43359

llvm-svn: 43353

llvm-svn: 43191

llvm-svn: 40757

llvm-svn: 38535

llvm-svn: 38516

_GLIBCXX_DEBUG.

llvm-svn: 37793

llvm-svn: 37633

llvm-svn: 37511

is too slow.

llvm-svn: 37509

llvm-svn: 37427

llvm-svn: 37408

llvm-svn: 37394

See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark.  I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.

llvm-svn: 37392

Do not remove empty landing pads (EH table needs to be updated)

llvm-svn: 37375

llvm-svn: 37355

matter until my last change).  Reenable tail merging by default.

llvm-svn: 37354