callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.

llvm-svn: 178391

registers.

llvm-svn: 178390

llvm-svn: 178368

Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).

Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.

llvm-svn: 178362

llvm-svn: 178359

It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

llvm-svn: 178349

llvm-svn: 178345

These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.

llvm-svn: 178337

register classes for Mips64 and DSP-ASE.

No functionality changes.

llvm-svn: 178328

No functionality changes.

llvm-svn: 178327

No functionality changes.

llvm-svn: 178326

Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic
llvm-svn: 178316

llvm-svn: 178314

- RDRAND always clears the destination value when a random value is not
  available (i.e. CF == 0). This value is truncated or zero-extended as
  the false boolean value to be returned. Boolean simplification needs
  to skip this 'zext' or 'trunc' node.

llvm-svn: 178312

To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.

To prevent that, such moving is disabled when target favors register
indirect call.

Previous workaround disabling CALL32m/CALL64m insn selection is removed.

llvm-svn: 178308

Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic
llvm-svn: 178304

llvm-svn: 178303

llvm-svn: 178301

llvm-svn: 178300

llvm-svn: 178299

llvm-svn: 178293

llvm-svn: 178291

Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).

llvm-svn: 178286

llvm-svn: 178281

Thanks to Bill Schmidt for pointing this out!

llvm-svn: 178280

llvm-svn: 178279

This follows up Ulrich Weigand's work in PPCInstrInfo.td and
PPCInstr64Bit.td by doing the corresponding work for most of the
Altivec patterns.  I have not been able to do anything for the
following classes of instructions:

(1) Vector logicals.  These don't have corresponding intrinsics and
don't have a single obvious vector type.  So far as I can tell I need
to leave these as VRRC.  Affected instructions are:  VAND, VANDC,
VNOR, VOR, VXOR, V_SET0.

(2) Instructions that make use of vector shuffle.  The selection code
promotes all shuffles to v16i8, so any pattern that matches on a
shuffle is constrained.  I haven't found any way to make the patterns
match on their natural types, so I plan to leave these as VRRC.
Affected instructions are:  VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM,
VPKUWUM.

No change in behavior is anticipated.

llvm-svn: 178277

These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.

llvm-svn: 178276

They should always be zero-extended, not sign extended.  Added test case.

llvm-svn: 178275

llvm-svn: 178256

Remove noV4T gp-relative instructions.

llvm-svn: 178246

llvm-svn: 178236

PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.

llvm-svn: 178233

There were a few places where kill flags were not being set correctly, and
where 32-bit instruction variants were being used with 64-bit registers. After
r178180, this code was being triggered causing llc to assert.

llvm-svn: 178220

llvm-svn: 178219

form of call in preference to memory indirect on Atom.

In this case, the patch applies the optimization to the code for reloading
spilled registers.

The patch also includes changes to sibcall.ll and movgs.ll, which were
failing on the Atom buildbot after the first patch was applied.

This patch by Sriram Murali.

llvm-svn: 178193

expression.  Specifically, this syntax:

 ImmDisp [ BaseReg + Scale*IndexReg + Disp ] 

We don't currently support:

 ImmDisp [ Symbol ]

rdar://13518671

llvm-svn: 178186

These functions should have the same list of load/store instructions. Now that
all load/store forms have been normalized (to single instructions or pseudos)
they can be resynchronized.

Found by inspection, although hopefully this will improve optimization.  I've
also added some comments.

llvm-svn: 178180

For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.

Patch by Sriram Murali.

llvm-svn: 178171

Thanks to Bill Schmidt for pointing this out during code review!

llvm-svn: 178170