llvm-svn: 147519

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

The patch and test case were originally written by Mans Rullgard.

llvm-svn: 147024

instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015

only when the target ABI is N64.

llvm-svn: 147001

only when the target ABI is N64. 

llvm-svn: 146992

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

llvm-svn: 146896

-relocation-model=static.

llvm-svn: 146432

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

RDHWR. 

llvm-svn: 146101

llvm-svn: 146081

llvm-svn: 146059

llvm-svn: 145912

them.

llvm-svn: 145852

- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113

nodes.

llvm-svn: 144841

llvm-svn: 144840

"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 143994

instruction definitions.

llvm-svn: 143989

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226

llvm-svn: 142220

llvm-svn: 142216

llvm-svn: 142214

llvm-svn: 142211

source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210

and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207

llvm-svn: 142205

llvm-svn: 141761

Remove unused classes.

llvm-svn: 141757

llvm-svn: 141743

instructions with two register operands derive from it.

llvm-svn: 141742

llvm-svn: 141737

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736