llvm-svn: 75188

Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.

Note, we are not yet generating these instructions.

llvm-svn: 75181

llvm-svn: 75172

llvm-svn: 75067

Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.

llvm-svn: 75048

llvm-svn: 75036

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

llvm-svn: 74946

llvm-svn: 74895

llvm-svn: 74889

llvm-svn: 74868

llvm-svn: 74755

llvm-svn: 74749

llvm-svn: 74741

llvm-svn: 74740

llvm-svn: 74736

llvm-svn: 74696

Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.

llvm-svn: 74692

llvm-svn: 74577

llvm-svn: 74566

llvm-svn: 74555

llvm-svn: 74549

llvm-svn: 74543

llvm-svn: 74500

llvm-svn: 74468

Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.

llvm-svn: 74423

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 74368

llvm-svn: 74357

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

llvm-svn: 74321

llvm-svn: 74293

Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288

llvm-svn: 74237

llvm-svn: 74228

llvm-svn: 74223

llvm-svn: 74200

Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.

llvm-svn: 74158

llvm-svn: 74156

llvm-svn: 74141