llvm-svn: 25307

llvm-svn: 25296

llvm-svn: 25293

flipped around.

llvm-svn: 25290

llvm-svn: 25278

llvm-svn: 25272

llvm-svn: 25263

llvm-svn: 25261

llvm-svn: 25260

llvm-svn: 25259

llvm-svn: 25257

ExternalSymbol to TargetExternalSymbol.

llvm-svn: 25253

linked together).

llvm-svn: 25247

  LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246

llvm-svn: 25232

llvm-svn: 25226

llvm-svn: 25225

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207

llvm-svn: 25192

llvm-svn: 25191

llvm-svn: 25190

* fiadd, fisub, etc.

llvm-svn: 25189

llvm-svn: 25188

* Some reorg.

llvm-svn: 25163

llvm-svn: 25162

llvm-svn: 25160

llvm-svn: 25158

* Fixed a load folding bug.

llvm-svn: 25136

llvm-svn: 25132

llvm-svn: 25129

llvm-svn: 25123

llvm-svn: 25120

* FP cmp, setcc, etc.

llvm-svn: 25117

llvm-svn: 25108

llvm-svn: 25105

inserted in the code.

llvm-svn: 25104

llvm-svn: 25103

llvm-svn: 25024

Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017