llvm-svn: 115348

The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.

llvm-svn: 115126

pipeline forwarding path.

llvm-svn: 115098

llvm-svn: 115096

operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up.  This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'

llvm-svn: 115019

llvm-svn: 115005

llvm-svn: 114847

llvm-svn: 114750

reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710

Not intended functionality change, as nothing uses this yet.

llvm-svn: 114702

llvm-svn: 114659

Explicitly cast arguments to the type the builtin expects, which is <vN x i8>

llvm-svn: 114596

that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.

llvm-svn: 114489

matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.

llvm-svn: 114472

passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471

llvm-svn: 114435

llvm-svn: 114433

llvm-svn: 114293

functions, since int64 is not a legal type and using it leads to inefficient
code.  PR8036.

llvm-svn: 113919

llvm-svn: 113865

This may produce warnings on MSVS, but it's better than failures.

llvm-svn: 113834

llvm-svn: 113671

instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

llvm-svn: 113422

llvm-svn: 113261

llvm-svn: 113250

Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233

llvm-svn: 113198

llvm-svn: 113197

is busted for all variants, report it as the location.  This allows
us to get the operand right for bugs like:

t.s:3:12: error: invalid operand for instruction
	outb %al, %gs
	          ^

Even though there are reg/imm and reg/reg forms of this instruction.

llvm-svn: 113183

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176

llvm-svn: 113174

llvm-svn: 113173

llvm-svn: 113172

by doing a binary search over the mnemonic instead of doing a linear
search through all possible instructions.  This implements rdar://7785064

llvm-svn: 113171

MatchInstructionImpl. This makes it easier to read/understand
MatchInstructionImpl.

llvm-svn: 113170

generated matcher, emiting it as a column in the MatchEntry
table instead of forcing it to go through classification and
everything else.  Making it be classified caused tblgen to
produce a ton of one-off classes for each mneumonic.  This
should reduce the size of the generated matcher significantly
while paving the way for future improvements.

llvm-svn: 113169

so only do the N^2 loop with debug mode.

llvm-svn: 113168