llvm-svn: 26504

llvm-svn: 26503

llvm-svn: 26502

llvm-svn: 26501

llvm-svn: 26500

llvm-svn: 26499

llvm-svn: 26498

llvm-svn: 26497

llvm-svn: 26496

llvm-svn: 26495

llvm-svn: 26494

llvm-svn: 26493

llvm-svn: 26492

llvm-svn: 26491

llvm-svn: 26490

llvm-svn: 26489

llvm-svn: 26488

llvm-svn: 26487

llvm-svn: 26486

llvm-svn: 26485

llvm-svn: 26484

llvm-svn: 26483

llvm-svn: 26482

llvm-svn: 26481

llvm-svn: 26480

llvm-svn: 26479

llvm-svn: 26478

into types.

llvm-svn: 26477

PR709, and paving the way for future progress.

llvm-svn: 26476

llvm-svn: 26475

PR709, and paving the way for future progress.

Significantly refactor autoupgrading code, to handle the more complex case
(where we upgrade one argument in a function), and fix some bugs in it.

Testcase here: llvm/test/Regression/Bytecode/memcpy.ll

llvm-svn: 26474

llvm-svn: 26473

llvm-svn: 26472

llvm-svn: 26471

  a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.

llvm-svn: 26470

pointed out: realize the AND can provide factors and look through Casts.

llvm-svn: 26469

llvm-svn: 26468

pointing this out.

llvm-svn: 26467

llvm-svn: 26466

llvm-svn: 26465