1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599

being shifted.  Don't assume they are.

llvm-svn: 24598

if available

llvm-svn: 24597

llvm-svn: 24596

Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.

llvm-svn: 24595

amount, which is not necessarily the same as the type being shifted.

llvm-svn: 24594

llvm-svn: 24593

llvm-svn: 24592

improvements.

llvm-svn: 24591

llvm-svn: 24590

llvm-svn: 24589

llvm-svn: 24588

* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587

  chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586

llvm-svn: 24585

llvm-svn: 24584

llvm-svn: 24583

llvm-svn: 24582

llvm-svn: 24581

llvm-svn: 24580

llvm-svn: 24579

This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

llvm-svn: 24578

llvm-svn: 24577

from .bc files.

llvm-svn: 24575

llvm-svn: 24574

llvm-svn: 24573

llvm-svn: 24572

should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll

llvm-svn: 24571

llvm-svn: 24570

Attempting to run it will find lli's main, which isn't the desired effect.

llvm-svn: 24569

llvm-svn: 24568

stuff isn't using ISelLowering.cpp

llvm-svn: 24567

llvm-svn: 24566

selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.

llvm-svn: 24565

llvm-svn: 24564

work.  This change has no effect on generated code.

llvm-svn: 24563

llvm-svn: 24562

llvm-svn: 24561

llvm-svn: 24560

llvm-svn: 24559