to unfold loop-invariant loads.

llvm-svn: 85657

that uses this information knows to behave conservatively.

llvm-svn: 85654

llvm-svn: 85653

llvm-svn: 85648

llvm-svn: 85639

results. This works around a problem affecting targets which rely on
MVT::Flag to handle physical register defs.

llvm-svn: 85638

unfolding loads for hoisting.  getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.

llvm-svn: 85622

llvm-svn: 85599

llvm-svn: 85572

llvm-svn: 85571

llvm-svn: 85562

llvm-svn: 85559

llvm-svn: 85558

llvm-svn: 85556

Between scheduling regions, correctly maintain anti-dep breaking state so that we don't incorrectly rename registers that span these regions.

llvm-svn: 85537

llvm-svn: 85536

*ISelDAGToDAG.cpp to being regular code in SelectionDAGISel.cpp.

llvm-svn: 85530

llvm-svn: 85522

llvm-svn: 85519

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

llvm-svn: 85515

llvm-svn: 85514

indexed via the stack pointer, even if a frame pointer is present. Update the
heuristic to place it nearest the stack pointer in that case, rather than
nearest the frame pointer.

llvm-svn: 85474

the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

llvm-svn: 85463

llvm-svn: 85460

--- Reverse-merging r85338 into '.':
U    lib/CodeGen/SimpleRegisterCoalescing.cpp
U    lib/CodeGen/SimpleRegisterCoalescing.h

llvm-svn: 85454

common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.

llvm-svn: 85441

to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec).  We need to
remove the store in this case.  Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here.  7331562.

llvm-svn: 85437

llvm-svn: 85436

I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426

llvm-svn: 85412

chains have no users, they can't be predecessors of the condition.

llvm-svn: 85394

the new instructions and leave the old one in place.

llvm-svn: 85393

recursive to avoid consuming extraordinary amounts of stack space
when processing tall graphs.

llvm-svn: 85369

otherwise unhoistable instructions in order to allow the loads
to be hoisted.

llvm-svn: 85364

llvm-svn: 85361

MachineLICM and other things which run before LiveVariables is run.

llvm-svn: 85360

if they have compatible encodings.

llvm-svn: 85359

llvm-svn: 85351

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346