llvm-svn: 192504

llvm-svn: 192499

llvm-svn: 192492

llvm-svn: 192487

This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483

When if converting something like:
true:
   ... = R0<kill>

false:
   ... = R0<kill>

then the instructions of the true block must not have a <kill> flag
anymore, as the instruction of the false block follow and do still read
the R0 value.
Specifically this patch determines the set of register live-in in the
false block (possibly after simulating the liveness changes of the
duplicated instructions). Each of these live-in registers mustn't be
killed.

llvm-svn: 192482

This should fix the buildbots.

Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32

into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>

llvm-svn: 192476

llvm-svn: 192474

other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
 a = load i64* addr
 b = trunc i64 a to i32
 c = lshr i64 a, 32
 d = trunc i64 c to i32

into:
 b = load i32* addr1
 d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>

llvm-svn: 192471

llvm-svn: 192460

llvm-svn: 192458

llvm-svn: 192455

llvm-svn: 192451

llvm-svn: 192450

llvm-svn: 192449

INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.

llvm-svn: 192447

[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc

Fixes PR17529

llvm-svn: 192445

Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs

For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers,
while NVPTX uses virtual registers (with a couple of exceptions).  Now, the implicit def comment will be
emitted as a true PTX register name. Other targets can use this to customize the output of implicit def
comments.

Fixes PR17519

llvm-svn: 192444

[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics)

llvm-svn: 192438

llvm-svn: 192435

llvm-svn: 192434

llvm-svn: 192433

When a ConstantExpr which uses a thread local is part of a PHI node
instruction, the insruction that replaces the ConstantExpr must
be inserted in the predecessor block, in front of the terminator instruction.
If the predecessor block has multiple successors, the edge is first split.

llvm-svn: 192432

llvm-svn: 192431

llvm-svn: 192430

[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics)

llvm-svn: 192429

llvm-svn: 192421

llvm-svn: 192410

llvm-svn: 192406

llvm-svn: 192398

Previously LiveInterval has been used, but having a spill weight and
register number is unnecessary for a register unit.

llvm-svn: 192397

Also change some pointer arguments to references at some places where
0-pointers are not allowed.

llvm-svn: 192396

llvm-svn: 192395

This makes the API a bit more natural to use and makes it easier to make
LiveRanges implementation details private.

llvm-svn: 192394

LiveRange just manages a list of segments and a list of value numbers
now as LiveInterval did previously, but without having details like spill
weight or a fixed register number.
LiveInterval is now a subclass of LiveRange and simply adds the spill weight
and the register number.

llvm-svn: 192393

The Segment struct contains a single interval; multiple instances of this struct
are used to construct a live range, but the struct is not a live range by
itself.

llvm-svn: 192392

llvm-svn: 192391

llvm-svn: 192386

DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192378

llvm-svn: 192375