Russell Wallace.

llvm-svn: 96580

out by Russell Wallace.

llvm-svn: 96579

Also, have tools output -help-hidden rather than refer to --help-hidden,
for consistency, and likewise adjust documentation.  This doesn't change
every mention of --help, only those which seemed clearly safe.

llvm-svn: 96578

llvm-svn: 96574

Radar 7461718.

llvm-svn: 96572

of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.

llvm-svn: 96565

Transform br (xor (x, y)) -> br (x != y)
Transform br (xor (xor (x,y), 1)) -> br (x == y)
Also normalize (and (X, 1) == / != 1 -> (and (X, 1)) != / == 0 to match to "test on x86" and "tst on arm"

llvm-svn: 96556

llvm-svn: 96540

llvm-svn: 96532

since it has no pattern, there's not much point in distinguishing an "N2VS"
class for intrinsics anyway.

llvm-svn: 96525

A8.6.30

llvm-svn: 96523

* Use "S" abbreviation for scalar single FP registers in class and pattern
names, instead of keeping the "D" (for "double") abbreviation and tacking on
an "s" elsewhere in the name.
* Move the scalar single FP register classes and patterns to be more
consistent with other definitions in the file.
* Rename "VNEGf32d" definition to "VNEGfd" for consistency.
* Deleted the N2VDIntsPat pattern; N2VSPat is good enough.

llvm-svn: 96521

B6.1.8 RFE Return From Exception loads the PC and the CPSR from the word at the
specified address and the following word respectively.

llvm-svn: 96519

Make the non-temporal bit "significant" in MemSDNodes so they aren't
CSE'd or otherwise combined with temporal MemSDNodes.

llvm-svn: 96505

llvm-svn: 96504

llvm-svn: 96503

llvm-svn: 96496

"Fix and issue in SparcAsmPrinter where multiple identical .LLGETPCHn symbols could be emitted in the same file (it was uniqued by block number, but not by function number). "  Patch by Nathan Keynes!

llvm-svn: 96495

and add a sparc implementation that knows about delay slots.  Patch by
Nathan Keynes!

llvm-svn: 96492

llvm-svn: 96490

cloned functions.

llvm-svn: 96485

cases that are not part of the enum.

llvm-svn: 96477

with mangled names).

llvm-svn: 96465

Renamed PIC16FrameOverlay namespace to PIC16OVERLAY.
Renamed PIC16FrameOverlay class to PIC16Overlay.

llvm-svn: 96463

A8.6.18  BFI - Bitfield insert (Encoding A1)

llvm-svn: 96462

tblgen splatted code into the implementation.

llvm-svn: 96460

reverse engineering what they are.

llvm-svn: 96456

Hopefully, this will fix the remaining issues seen there.

llvm-svn: 96454

Removed an early out which was causing the PBQP allocator to not compute live-in sets or run the rewriter.

llvm-svn: 96450

case where there are loop-invariant instructions somehow left
inside the loop, and in a position where they won't dominate
the IV increment position.

llvm-svn: 96448

Before setting scope end marker, pay attention to scope begin marker and existing scope end marker, if any. Scope must begin before it ends and nested inlined scope do not truncate surrounding scope.

llvm-svn: 96445

llvm-svn: 96440

It's not clear why this is really required, but it was explicitly
added in r48808 with no real explanation or rdar #.

llvm-svn: 96438

This pass is supposed to be run on the linked .bc module.
It traveses the module call graph twice. Once starting from the main function
and marking each reached function as "ML". Again, starting from the ISR
and cloning any reachable function that was marked as "ML". After cloning
the function, it remaps all the call sites in IL functions to call the
cloned functions. 

Currently only marking is being done.

llvm-svn: 96435

llvm-svn: 96432

llvm-svn: 96429

have overflowed.

llvm-svn: 96428

64 bits, fixing a variety of problems.

llvm-svn: 96421

indentation.  No functional changes.

llvm-svn: 96418

llvm-svn: 96410