llvm-svn: 136480

Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479

llvm-svn: 136478

llvm-svn: 136477

Renamed Loaded member to ImportedBy, as it's easier to read.  Added another set to represent the modules a module imports.

llvm-svn: 136476

llvm-svn: 136475

llvm-svn: 136473

llvm-svn: 136472

llvm-svn: 136470

llvm-svn: 136469

llvm-svn: 136468

llvm-svn: 136467

llvm-svn: 136463

llvm-svn: 136461

whatever the size of unsigned is), though this can't actually
occur for any integer value of NUM_NODES.

llvm-svn: 136460

screwy things by setting PWD != getcwd(). For example, some developers I know
will use this to control the value in gcc's DW_AT_comp_dir value in debug
output. With this patch, that trick will now work on clang too.

The only other effect of this change is that the static analysis will now
respect $PWD when reporting the directory of the files in its HTML output. I
think that's fine.

llvm-svn: 136459

lines. No functionality change.

llvm-svn: 136458

working on x86 (at least for trivial testcases); other architectures will
need more work so that they actually emit the appropriate instructions for
orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC,
Mips, and Alpha backends need such changes.)

llvm-svn: 136457

rounding errors.

llvm-svn: 136456

First off, only depend on the actual MC-ized disassemblers in the
targets, not all of the libraries those in turn depend on.

Second off, only depend on those MC-ized disassemblers for targets we're
building.

This should fix builds of fewer than all targets.

llvm-svn: 136455

on the second half must be reindexed.

llvm-svn: 136454

generation to always catch the weird cases.

llvm-svn: 136453

llvm-svn: 136452

llvm-svn: 136451

undef mask elements. This fixes PR10529.

llvm-svn: 136450

Also tidy up code a bit.

llvm-svn: 136449

Also make PALIGNR masks to don't match 256-bits, which isn't supported
It's also a step to solve PR10489

llvm-svn: 136448

DiagnosticErrorTraps can be composed (e.g. a trap inside another trap).

Fixes http://llvm.org/PR10462 & rdar://9852007.

llvm-svn: 136447

With this, we can now compile a simple EH program.

llvm-svn: 136446

llvm-svn: 136445

llvm-svn: 136444

C++98/03, and C++0x mode, from Craig Topper!

llvm-svn: 136443

llvm-svn: 136442

were (Module*, Offset) with equivalent maps whose value type is just a
Module*. The offsets have moved into corresponding "Base" fields
within the Module itself, where they will also be helpful for
local->global translation (eventually).

llvm-svn: 136441

Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440

This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439

instruction is tied to an output operand which is a pointer, and
the input operand is narrower than the output operand.

llvm-svn: 136438

the callee note diagnostic was not emitted in the case where
there were too few arguments.

llvm-svn: 136437

Module itself, which makes more sense. This pattern to be repeated
several more times.

llvm-svn: 136436

Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>

llvm-svn: 136435