llvm-svn: 33780

llvm-svn: 33741

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

llvm-svn: 33727

llvm-svn: 33724

llvm-svn: 33721

ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.

llvm-svn: 33703

that would require > 3 instructions to materialize), load the immediate from a
constpool entry.

llvm-svn: 33667

sp, imm instructions implicitly multiply the offset by 4.

llvm-svn: 33653

llvm-svn: 33652

  spilled (if it is not already).
- If LR is spilled, use BL to implement far jumps. LR is not used as a GPR
  in thumb mode so it can be clobbered if it is properly spilled / restored
  in prologue / epilogue.
- If LR is force spilled but no far jump has been emitted, try undo'ing the
  spill by:
  push lr -> delete
  pop pc -> bx lr

llvm-svn: 33650

llvm-svn: 33632

llvm-svn: 33551

llvm-svn: 33509

PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.

llvm-svn: 33460

llvm-svn: 33455

llvm-svn: 33401

llvm-svn: 33390

llvm-svn: 33389

llvm-svn: 33366

llvm-svn: 33353

llvm-svn: 33142

llvm-svn: 33141

llvm-svn: 32823

Lauros's patch

llvm-svn: 32656

patch by Lauro

llvm-svn: 32577

llvm-svn: 32333

of opcode and number of operands.

llvm-svn: 31947

remove lea_addri and the now unused memri addressing mode

llvm-svn: 31592

TODO: fix lea_addri

llvm-svn: 31552

llvm-svn: 31312

llvm-svn: 31197

llvm-svn: 30998

llvm-svn: 30995

llvm-svn: 30766

llvm-svn: 30291

llvm-svn: 30252

def operand or a use operand.

llvm-svn: 30109

llvm-svn: 29748

Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727