llvm-svn: 162892

- The root cause is that target constant materialization in X86 fast-isel
  creates a PC-rel addressing which may overflow 32-bit range in non-Small code
  model if .rodata section is allocated too far away from code segment in
  MCJIT, which uses Large code model so far.
- Follow the similar logic to fix non-Small code model in fast-isel by skipping
  non-Small code model.

llvm-svn: 162881

llvm-svn: 162843

llvm-svn: 162829

llvm-svn: 162807

llvm-svn: 162805

llvm-svn: 162780

it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>

llvm-svn: 162741

llvm-svn: 162740

llvm-svn: 162738

- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
  Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
  X86ISD::OR node has only its flag result being used as a boolean value and
  all its leaves are extracted from the same vector, it could be folded into an
  X86ISD::PTEST node.

llvm-svn: 162735

llvm-svn: 162714

llvm-svn: 162661

Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur.

llvm-svn: 162658

Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'

llvm-svn: 162656

Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.

llvm-svn: 162654

Reviewed offline by chandlerc.

llvm-svn: 162623

llvm-svn: 162622

There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

llvm-svn: 162592

llvm-svn: 162556

llvm-svn: 162534

They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

llvm-svn: 162517

llvm-svn: 162514

No test case, this is a generalization of r160260.

llvm-svn: 162485

llvm-svn: 162454

llvm-svn: 162428

Assertion failed: (Start.isValid() == End.isValid() && "Start and end should 
either both be valid or both be invalid!")

when parsing inline asm.  SMLoc assumes that the first char * in the source is
invalid.  However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.

llvm-svn: 162381

Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.

llvm-svn: 162347

Don't cache the MBB in the class. Its only used by one function. Change a for loop over operands to use unsigned instead of int.

llvm-svn: 162344

llvm-svn: 162342

no cost to using memcpy here: the fixed code is optimized by LLVM to perfect
machine code.

llvm-svn: 162311

llvm-svn: 162306

this is the index of the operand that failed to match.

Note: This may cause a buildbot failure due to an API mismatch in clang.  Should
recover with my next commit to clang.

llvm-svn: 162295

llvm-svn: 162270

llvm-svn: 162267

llvm-svn: 162264

llvm-svn: 162263

Replace a break with llvm_unreachable in the default case of a nested switch. Condense code a bit. No functional change.

llvm-svn: 162261

llvm-svn: 162260

llvm-svn: 162257