alignment information appropriately.  Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack.  Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224

llvm-svn: 23559

class into the spill/reload methods.  Targets can now rely on that argument.

llvm-svn: 23556

code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.

llvm-svn: 23536

Olden/bisort among others.

llvm-svn: 23124

llvm-svn: 23108

terminator instructions before the 'ret' in case the target has a
multi-instruction return sequence.

llvm-svn: 22041

llvm-svn: 21982

llvm-svn: 21420

registers.  This information is computed directly by the register allocator
now.

llvm-svn: 19795

llvm-svn: 19787

This fixes the return-address-not-being-saved problem in the Alpha backend.

llvm-svn: 19741

llvm-svn: 19704

Put this change back in after testing from Reid proved its innocence.  getSpillSize now returns value in bits

llvm-svn: 16102

Back out change to divide getSpillSize by 8 until I figure out why it breaks x86, which has register sizes in bits.

llvm-svn: 16073

llvm-svn: 16070

bytes.

llvm-svn: 15970

of getRegClass

llvm-svn: 15967

llvm-svn: 15775

llvm-svn: 15774

allowed).

llvm-svn: 15766

llvm-svn: 15736

Add support for targets that must spill certain physregs at certain locations.

Patch contributed by Nate Begeman, slightly hacked by me.

llvm-svn: 15701

llvm-svn: 15564

llvm-svn: 15563

printed incorrectly, and we were reserving 8 extra bytes of stack space for functions
on X86.

llvm-svn: 14152

targets whose stack grows up.

Patch contributed by Vladimir Prus

llvm-svn: 14111

llvm-svn: 13956

MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.

llvm-svn: 11477

clobber them by allocating other objects in the same space!

llvm-svn: 11454

llvm-svn: 11449

ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

llvm-svn: 11283

llvm-svn: 11278

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

llvm-svn: 9903

Header files will be on the way.

llvm-svn: 9298

and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}

llvm-svn: 8960

llvm-svn: 7823

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341