llvm-svn: 170057

FFR2P_M.
 

llvm-svn: 170055

 

llvm-svn: 170054

FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053

llvm-svn: 170052

Teach the cost model about the optimization in r169904: Truncation of induction variables costs the same as scalar trunc. 

llvm-svn: 170051

llvm-svn: 170050

Make the MCStreamer have a reset method and call that after finalization of the asm printer, 
also changed MCContext to a single reset only method for simplicity as requested on the list

llvm-svn: 170041

should only occur on invalid input.  Instruction matching errors aren't
unexpected, so we can't rely on the AsmParsers HadError variable directly.
rdar://12840278

llvm-svn: 170037

YAMLIO: Remove all of the template instantiation hacks, I don't see why they're necessary and it breaks linking of the unit tests.

Also comes with a clang-format run on the cpp file, it had major style violations.

llvm-svn: 170036

llvm-svn: 170030

llvm-svn: 170024

llvm-svn: 170022

llvm-svn: 170021

llvm-svn: 170020

structures to and from YAML using traits.  The first client will
be the test suite of lld.  The documentation will show up at:

   http://llvm.org/docs/YamlIO.html

llvm-svn: 170019

load / store pair. It's not legal to use a wider load than the size of
the remaining bytes if it's the first pair of load / store.

llvm-svn: 170018

llvm-svn: 170012

llvm-svn: 170007

llvm-svn: 170005

LoopVectorizer: Use the "optsize" attribute to decide if we are allowed to increase the function size.

llvm-svn: 170004

PowerPC target.  This is the last of the four models, so we now have 
full TLS support.

This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.

As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly.  The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.

There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.

Bill

llvm-svn: 170003

llvm-svn: 170002

been used in the first place.  It simply was passed to the function and to the
recursive invocations.  Simply drop the parameter and update the callers for the
new signature.

Patch by Saleem Abdulrasool!

llvm-svn: 169988

When ASan replaces <alloca instruction> with
<offset into a common large alloca>, it should also patch
llvm.dbg.declare calls and replace debug info descriptors to mark
that we've replaced alloca with a value that stores an address
of the user variable, not the user variable itself.

See PR11818 for more context.

llvm-svn: 169984

Add R_ARM_NONE and R_ARM_PREL31 relocation types
to MCExpr.  Both of them will be used while
generating .ARM.extab and .ARM.exidx sections.

llvm-svn: 169965

llvm-svn: 169963

llvm-svn: 169962

mention the inline memcpy / memset expansion code is a mess?

This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.

llvm-svn: 169959

llvm-svn: 169955

Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.

llvm-svn: 169954

llvm-svn: 169953

rdar://12838504

llvm-svn: 169951

LoopVectorizer: When -Os is used, vectorize only loops that dont require a tail loop. There is no testcase because I dont know of a way to initialize the loop vectorizer pass without adding an additional hidden flag. 

llvm-svn: 169950

f64 load / store on non-SSE2 x86 targets.

llvm-svn: 169944

llvm-svn: 169943

- Propagate "exact" bit of [l|a]shr instruction.

llvm-svn: 169942

Remove redunant optimizations from InstCombine, instead call the appropriate functions from SimplifyInstruction

llvm-svn: 169941

Added a slew of SimplifyInstruction floating-point optimizations, many of which take advantage of fast-math flags. Test cases included.

  fsub X, +0 ==> X
  fsub X, -0 ==> X, when we know X is not -0
  fsub +/-0.0, (fsub -0.0, X) ==> X
  fsub nsz +/-0.0, (fsub +/-0.0, X) ==> X
  fsub nnan ninf X, X ==> 0.0
  fadd nsz X, 0 ==> X
  fadd [nnan ninf] X, (fsub [nnan ninf] 0, X) ==> 0
    where nnan and ninf have to occur at least once somewhere in this expression
  fmul X, 1.0 ==> X

llvm-svn: 169940

llvm-svn: 169933