Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.

llvm-svn: 164204

llvm-svn: 164199

Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164191

Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164190

This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

llvm-svn: 164189

llvm-svn: 164165

Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.

llvm-svn: 164109

Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space.

llvm-svn: 164108

Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105

llvm-svn: 164097

llvm-svn: 164096

TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

llvm-svn: 164095

llvm-svn: 164094

llvm-svn: 164092

llvm-svn: 164088

llvm-svn: 164086

llvm-svn: 164078

llvm-svn: 164075

I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072

llvm-svn: 164066

llvm-svn: 164064

llvm-svn: 164063

TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

llvm-svn: 164062

llvm-svn: 164061

llvm-svn: 164060

Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059

llvm-svn: 164058

llvm-svn: 164057

Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

llvm-svn: 164041

The cases where no initialization happens should still be checked for logic flaws.

llvm-svn: 164032

llvm-svn: 164012

llvm-svn: 164002

llvm-svn: 163999

parameters.

llvm-svn: 163984

Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed.

llvm-svn: 163959

Collect processor resources from the subtarget defs.

llvm-svn: 163953

Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952

Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951

Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands.

llvm-svn: 163880

Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.

llvm-svn: 163878