llvm-svn: 67811

llvm-svn: 67798

llvm-svn: 67784

Detailed bug report:
http://llvm.org/bugs/show_bug.cgi?id=3873

llvm-svn: 67768

llvm-svn: 67765

llvm-svn: 67764

llvm-svn: 67742

llvm-svn: 67739

llvm-svn: 67738

llvm-svn: 67737

llvm-svn: 67736

  %a = ...
  %b = and i32 %a, 2
  %c = srl i32 %b, 1
  %d = br i32 %c, 

into

  %a = ...
  %b = and %a, 2
  %c = X86ISD::CMP %b, 0
  %d = X86ISD::BRCOND %c ...

This applies only when the AND constant value has one bit set and the SRL
constant is equal to the log2 of the AND constant. The back-end is smart enough
to convert the result into a TEST/JMP sequence.

llvm-svn: 67728

llvm-svn: 67727

called from llc, not opt, but it's an IR level
optimization nevertheless.)

llvm-svn: 67724

Before deleting a basic block, give other loop passes a chance cleanup analysis values, related to the instructions in the basic block.

llvm-svn: 67719

Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.

llvm-svn: 67701

stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.

llvm-svn: 67692

call, we should treat "i64 zext" as the start of a constant expr, but
"i64 0 zext" as an argument with an obsolete attribute on it (this form
is already tested by test/Assembler/2007-07-30-AutoUpgradeZextSext.ll).

Make the autoupgrade logic more discerning to avoid treating "i64 zext"
as an old-style attribute, causing us to reject a valid constant expr.
This fixes PR3876.

llvm-svn: 67682

llvm-svn: 67681

Do not ignore DW_TAG_class_type!

llvm-svn: 67675

llvm-svn: 67668

llvm-svn: 67667

precise than it used to be.

llvm-svn: 67662

llvm-svn: 67661

llvm-svn: 67657

llvm-svn: 67649

llvm-svn: 67642

to/from integer types that are not intptr_t to convert to intptr_t
then do an integer conversion to the dest type.  This exposes the
cast to the optimizer.

llvm-svn: 67638

and streamline code here a bit.

llvm-svn: 67636

1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1).  This 
   exposes the AND to other instcombine xforms and is more of what the code
   generator expects.
2. Rewrite the remaining trunc pattern match to use 'match', which 
   simplifies it a lot.
   

llvm-svn: 67635

llvm-svn: 67629

the target constraint specifies a specific physreg.

llvm-svn: 67618

llvm-svn: 67617

fail.

llvm-svn: 67616

to be returned in DL. LLVM's multiple-return-value support is
not ABI-conforming; front-ends that wish to have code emitted
that conforms to an ABI are currently expected to make
arrangements for this on their own rather than assuming that
multiple-return-values will automatically do the right thing.
This commit doesn't fundamentally change this situation.

llvm-svn: 67588

canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

llvm-svn: 67587

help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.

llvm-svn: 67586

llvm-svn: 67580

llvm-svn: 67578

Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.                                                                                                  
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574