llvm-svn: 134645

based on a modifier, split it into two functions.

llvm-svn: 134637

llvm-svn: 134633

llvm-svn: 134630

llvm-svn: 134629

llvm-svn: 134628

before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625

llvm-svn: 134622

llvm-svn: 134606

llvm-svn: 134281

llvm-svn: 134259

  itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257

llvm-svn: 134244

llvm-svn: 134224

be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127

llvm-svn: 134087

Part of rdar://9643582

llvm-svn: 134084

llvm-svn: 134049

llvm-svn: 134030

llvm-svn: 134027

llvm-svn: 134024

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

into XXXGenRegisterInfo.inc.

llvm-svn: 133922

 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

llvm-svn: 133811

static variables or functions. 

llvm-svn: 133803

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

handle functions with return type Complex long long.

llvm-svn: 133497

llvm-svn: 133496

llvm-svn: 133494

llvm-svn: 133118

This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781

llvm-svn: 132777

llvm-svn: 132768

No functional change.

Part of PR6965

llvm-svn: 132763

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132756

llvm-svn: 132726

llvm-svn: 132725

- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724