llvm-svn: 161143

llvm-svn: 161134

llvm-svn: 161133

llvm-svn: 161132

llvm-svn: 161122

llvm-svn: 161110

Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.

llvm-svn: 161101

No new test case is added.
This patch makes test JITTest.FunctionIsRecompiledAndRelinked pass on mips
platform.

Patch by Petar Jovanovic.

llvm-svn: 161098

llvm-svn: 161095

instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.

llvm-svn: 161093

MipsSERegisterInfo.

llvm-svn: 161092

MipsSEFrameLowering.

Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be
reserved if there is a call with a large call frame or there are variable sized
objects on the stack.

llvm-svn: 161090

llvm-svn: 161083

and MipsSEInstrInfo (for mips32/64).

llvm-svn: 161081

of them.

llvm-svn: 161080

computing it in MipsFrameLowering::emitPrologue.

llvm-svn: 161078

The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.

llvm-svn: 161076

or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071

instruction class. SE stands for standard encoding.

llvm-svn: 161069

arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.

llvm-svn: 161068

Previously, we were using EBX, but PIC requires the GOT to be in EBX before 
function calls via PLT GOT pointer.

llvm-svn: 161066

single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063

llvm-svn: 161029

llvm-svn: 161027

llvm-svn: 161026

where the other_half of the movt and movw relocation entries needs to get set
and only with the 16 bits of the other half.

rdar://10038370

llvm-svn: 160978

llvm-svn: 160953

Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.

llvm-svn: 160951

llvm-svn: 160942

llvm-svn: 160941

Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.

llvm-svn: 160939

llvm-svn: 160938

llvm-svn: 160937

llvm-svn: 160927

llvm-svn: 160922

llvm-svn: 160921

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276

llvm-svn: 160919

llvm-svn: 160914

llvm-svn: 160913

It is possible that an instruction can use and update EFLAGS.
When checking the safety, we should check the usage of EFLAGS first before
declaring it is safe to optimize due to the update.

llvm-svn: 160912