llvm-svn: 100849

a separate function.

llvm-svn: 100845

llvm-svn: 100841

be sent to LSR, which it isn't prepared to handle.

llvm-svn: 100839

forced constant is changed to a constant, we would end
up adding the instruction to the wrong worklist, 
preventing it from being properly revisited.  This fixes
rdar://7832370

llvm-svn: 100837

inputs happen to negate each other.

llvm-svn: 100828

llvm-svn: 100825

llvm-svn: 100824

llvm-svn: 100815

merge XCore's section into MCSectionELF

llvm-svn: 100812

api and update clients to use MCContext instead.

llvm-svn: 100808

the compiler and asmparser now unique to the same sections.  This fixes
rdar://7835021.

llvm-svn: 100807

%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

llvm-svn: 100804

llvm-svn: 100802

llvm-svn: 100799

unintended behavior.

llvm-svn: 100798

llvm-svn: 100797

implicit defs get added to the end of machine instrs sometimes.  Scan the whole instruction for the metadata operand instead of assuming it will be at the end of the instruction.

llvm-svn: 100792

llvm-svn: 100789

llvm-svn: 100787

There is no need to remember labels identifying regions marked by such instructions in each scope.

llvm-svn: 100781

llvm-svn: 100780

llvm-svn: 100774

llvm-svn: 100771

llvm-svn: 100769

llvm-svn: 100768

llvm-svn: 100767

llvm-svn: 100762

llvm-svn: 100760

llvm-svn: 100758

llvm-svn: 100756

llvm-svn: 100751

undef as 0, since it can't force other analyses to intepret the undef
in the same way.

llvm-svn: 100749

ensure that the expansion is dominated by the increments of those loops.

llvm-svn: 100748

llvm-svn: 100742

Fixes PR3440.

llvm-svn: 100736

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

llvm-svn: 100735

so the user at least knows what inline asm is a problem.  For example:

error: inline asm not supported yet: don't know how to handle tied indirect register inputs
pr8788-1.c:14:10: note: generated from here
    asm ("\n" : "+r" (stack->regs)
         ^

Instead of:
fatal error: error in backend: Don't know how to handle tied indirect register inputs yet!

llvm-svn: 100731

llvm-svn: 100725

llvm-svn: 100724