All but two patterns have been converted to the new syntax.  The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.

llvm-svn: 180922

Fortunately this pattern never matched, otherwise
we would have generated incorrect code.

Signed-off-by: Christian K??nig <christian.koenig@amd.com>
llvm-svn: 180921

This will improve the performance of memory reads.

llvm-svn: 180762

llvm-svn: 180761

llvm-svn: 180760

llvm-svn: 180759

llvm-svn: 180758

llvm-svn: 180757

llvm-svn: 180756

v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755

llvm-svn: 180753

llvm-svn: 180752

llvm-svn: 180751

llvm-svn: 180735

The EOP bit was not being encoded.

llvm-svn: 180734

We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620

Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231

The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230

llvm-svn: 180124

llvm-svn: 180123

The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064

llvm-svn: 179901

llvm-svn: 179830

InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829

llvm-svn: 179686

llvm-svn: 179685

llvm-svn: 179684

Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546

llvm-svn: 179545

llvm-svn: 179544

llvm-svn: 179263

llvm-svn: 179262

21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186

llvm-svn: 179174

Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179165

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164

llvm-svn: 179020

v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931

The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930