Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those

llvm-svn: 110769

Remove 256-bit unpack built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments

llvm-svn: 110768

llvm-svn: 110767

Remove 256-bit shuffle built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments

llvm-svn: 110766

llvm-svn: 110765

llvm-svn: 110764

llvm-svn: 110763

llvm-svn: 110762

llvm-svn: 110761

where we weren't accounting for the possibility that a @finally block might
have internal cleanups and therefore might write to the cleanup destination slot.

Fixes <rdar://problem/8293901>.

llvm-svn: 110760

llvm-svn: 110759

make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758

from inline assembly, except in cases where they had already been seen (in which
case they would get added twice).
 - I can't see how this ever worked...

llvm-svn: 110757

llvm-svn: 110756

Have GRCoreEngine record the blocks where analysis was aborted because we visited a block too many times along a given path.  This is to support the unreachable code analysis.

llvm-svn: 110755

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-config.h are included.

This is the cmake counterpart of r110547. See bug #7809.

llvm-svn: 110753

llvm-svn: 110752

llvm-svn: 110751

llvm-svn: 110750

llvm-svn: 110748

llvm-svn: 110745

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

create constraints from comparisons other than eq/neq.

llvm-svn: 110742

Add test case for <rdar://problem/8288645>.  While this is fixed in trunk, we previously were getting the following assertion failure not too long ago:

Assertion failed: (getContainingDC(DC) == CurContext && "The next DeclContext should be lexically contained in the current one.")

llvm-svn: 110740

llvm-svn: 110739

Something's wrong with this test on other platforms.  I'll probably need to simplify it later.  For now revert.

llvm-svn: 110738

llvm-svn: 110737

llvm-svn: 110736

llvm-svn: 110735

patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.

llvm-svn: 110734

a register before checking if it was defined.

llvm-svn: 110733

interpreter right before calling Py_Finalize().  This also fixed the crash as
reported in rdar://problem/8252903.

llvm-svn: 110731

operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

llvm-svn: 110730

llvm-svn: 110729

llvm-svn: 110726

llvm-svn: 110724

The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

llvm-svn: 110721

llvm-svn: 110720

handler similar to what's happening for the individual test case run.

llvm-svn: 110719