llvm-svn: 50383

the trip count.

llvm-svn: 50382

Fix a bug in RegsForValue::getCopyToRegs() that causes cyclical scheduling units. If it's creating multiple CopyToReg nodes that are "flagged" together, it should not create a TokenFactor for it's chain outputs:

c1, f1 = CopyToReg                                                                                                                                                                                             
c2, f2 = CopyToReg                                                                                                                                                                                             
c3     = TokenFactor c1, c2                                                                                                                                                                                    
 ...                                                                                                                                                                                                                      
       = user c3, ..., f2

Now that the two CopyToReg's and the user are "flagged" together. They effectively forms a single scheduling unit. The TokenFactor is now both an operand and a successor of the Flagged nodes.

llvm-svn: 50376

be truncated to 32 bits. This fixes the recent Benchmarks/McCat/09-vor
regression on x86-64, among other things.

llvm-svn: 50372

llvm-svn: 50370

if the zext is not legal.

llvm-svn: 50368

llvm-svn: 50367

aggregate types.

llvm-svn: 50366

reorder some of the members for clarity.

llvm-svn: 50365

Bug fix in BumpPtrAllocator: don't assume that all objects have the same alignment.  "Bump" of the pointer for the next allocated object to be of the specified alignment.

llvm-svn: 50362

llvm-svn: 50361

Patch by Anders Johnsen!

llvm-svn: 50360

memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.

llvm-svn: 50359

ComputeMaskedBits knows about cttz, ctlz, and ctpop. Teach
SelectionDAG's ComputeMaskedBits what InstCombine's knows
about SRem. And teach them both some things about high bits
in Mul, UDiv, URem, and Sub. This allows instcombine and
dagcombine to eliminate sign-extension operations in
several new cases.

llvm-svn: 50358

sign-bit of x is known to be zero.

llvm-svn: 50357

llvm-svn: 50355

llvm-svn: 50342

llvm-svn: 50341

conversion open the door for many nasty implicit conversion issues, and
can be easily solved by initializing with (V.begin(), V.end()) when 
needed.

This patch includes many small cleanups for sdisel also.

llvm-svn: 50340

heap thrash on tiny (usually single-element) vectors.

llvm-svn: 50335

multiple return values.

Bill, please pull this into Tak.

llvm-svn: 50332

llvm-svn: 50330

llvm-svn: 50329

llvm-svn: 50328

llvm-svn: 50325

llvm-svn: 50324

llvm-svn: 50316

When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible.  This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:

void test () {
  asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}

Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.

Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??

Incidentally, this was the todo in 
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll

Please do NOT pull this into Tak.

llvm-svn: 50315

llvm-svn: 50314

llvm-svn: 50313

  - Make targetlowering.h fit in 80 cols.
  - Make LowerAsmOperandForConstraint const.
  - Make lowerXConstraint -> LowerXConstraint
  - Make LowerXConstraint return a const char* instead of taking a string byref.

llvm-svn: 50312

the default impl.

llvm-svn: 50311

appropriate alignment.  This fixes a miscompilation of 252.eon on
x86-64 (rdar://5891920).

Bill, please pull this into Tak.

llvm-svn: 50308

llvm-svn: 50300

llvm-svn: 50292

llvm-svn: 50291

llvm-svn: 50289

to the block that defines their operands. This doesn't work in the
case that the operand is an invoke, because invoke is a terminator
and must be the last instruction in a block.

Replace it with support in SelectionDAGISel for copying struct values
into sequences of virtual registers.

llvm-svn: 50279

llvm-svn: 50278

function, and then use it to fix a bug in SplitVectorOp that expected inserts
to always have constant insertion indices.

llvm-svn: 50273