Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064

were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

llvm-svn: 105061

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

llvm-svn: 105014

llvm-svn: 105012

llvm-svn: 105009

as is done with most other cast opcode predicates.

llvm-svn: 105008

llvm-svn: 105006

llvm-svn: 105005

llvm-svn: 105001

getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994

llvm-svn: 104993

llvm-svn: 104992

implementation that is correct for most targets. Tablegen will override where
needed.

Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.

llvm-svn: 104985

llvm-svn: 104980

llvm-svn: 104974

llvm-svn: 104970

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

llvm-svn: 104963

llvm-svn: 104962

llvm-svn: 104961

llvm-svn: 104959

llvm-svn: 104958

llvm-svn: 104957

llvm-svn: 104956

llvm-svn: 104953

reference the stack.

llvm-svn: 104951

effective no-op constructs, to make it more effective on
unoptimized IR.

llvm-svn: 104950

lib/Transforms/Utils and into lib/Analysis so that Analysis passes
can use them.

llvm-svn: 104949

llvm-svn: 104948

llvm-svn: 104947

llvm-svn: 104945

llvm-svn: 104944

llvm-svn: 104936

llvm-svn: 104935

llvm-svn: 104927

llvm-svn: 104915

llvm-svn: 104914