llvm-svn: 108130

llvm-svn: 108071

 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039

notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996

U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987

llvm-svn: 107947

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

Debug info intrinsics win for now.

llvm-svn: 107850

in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825

around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791

The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

llvm-svn: 107529

list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

llvm-svn: 107520

llvm-svn: 106834

names for the array fields.

llvm-svn: 106803

llvm-svn: 106795

the array fields in these structs.

llvm-svn: 106794

llvm-svn: 106671

Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.

llvm-svn: 106670

Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey!

llvm-svn: 106620

a toplevel 'defm', make sure to properly resolve references.

llvm-svn: 106570

llvm-svn: 106470

Add support for returning multiple vectors via sret, which is how the ARM target expects the intrinsics to work.

llvm-svn: 106406

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.

llvm-svn: 106305

MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296

llvm-svn: 106246

llvm-svn: 106207

llvm-svn: 106201

be evaluated for 'bit' operators

llvm-svn: 106185

llvm-svn: 106179

llvm-svn: 106178

The attribute class generation support is still somewhat limited.
See the accompanying clang commit for more details.

llvm-svn: 106174

llvm-svn: 106171

llvm-svn: 106054

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

llvm-svn: 105970

llvm-svn: 105929

Add code for generating bits of semachecking

llvm-svn: 105907

warnings, and don't shift by a bool.  Patch by Rizky Herucakra!

llvm-svn: 105886

llvm-svn: 105874