This loop is quadratic in the capacity for a DenseMap:

  while(!map.empty())
    map.erase(map.begin());

Instead we now do a normal begin() - end() iteration followed by map.clear().
That also has the nice sideeffect of shrinking the map capacity on demand.

llvm-svn: 103747

Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.

llvm-svn: 103746

one was subject to double rounding in extreme cases.

llvm-svn: 103744

llvm-svn: 103739

llvm-svn: 103738

when they move instructions.

llvm-svn: 103737

llvm-svn: 103731

Do not use those for Thumb1 functions.

llvm-svn: 103730

Patch by Dimitry Andric!

llvm-svn: 103727

use of it in MachineCSE.

llvm-svn: 103726

basic block.

llvm-svn: 103725

llvm-svn: 103724

llvm-svn: 103715

MC: Move ordinal calculation, to make sure fragments synthesized for layout get assigned ordinals properly.

llvm-svn: 103711

llvm-svn: 103710

llvm-svn: 103709

llvm-svn: 103702

llvm-svn: 103700

vector<>::push_back() in:

  int foo(vector<int> &a, vector<unsigned> &b) {
    a.push_back(10);
    b.push_back(11);
  }

to two calls to the same push_back function, or fold away the two copies of
push_back() in:

  struct T { int; };
  struct S { char; };
  vector<T*> t;
  vector<S*> s;
  void f(T *x) { t.push_back(x); }
  void g(S *x) { s.push_back(x); }

but leave f() and g() separate, since they refer to two different global
variables.

llvm-svn: 103698

llvm-svn: 103697

utility functions.

llvm-svn: 103695

llvm-svn: 103694

of manually doing padding/editing layout in LayoutSection().
    - This probably seems like six-of-one and half-dozen of another, but there
      is a method to my madness.

llvm-svn: 103693

Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.

llvm-svn: 103692

MC: Add MCAlignFragment::OnlyAlignAddress bit. This is a bit of magic that says the align fragment shouldn't contribute to the logical section size, it is will be used for cleaning up the code to handle section alignment.

llvm-svn: 103690

MC: Add MCSectionData::AddressSize, which is the size of the address space consumed by the section. This can differ from both the section logical size, and the section size on disk (although the current code handles this without making an explicit distinction).

llvm-svn: 103689

This causes way more identity copies to be generated, ripe for coalescing.

llvm-svn: 103686

llvm-svn: 103685

llvm-svn: 103684

llvm-svn: 103683

ParseDirectiveDarwinZerofill instead of hard coding the
check for identifier. This allows quoted symbol names to
be used.

llvm-svn: 103682

after testing before committing.

llvm-svn: 103681

If REG_SEQUENCE source is livein, copy it first. Also, update livevariables information when a copy is introduced.

llvm-svn: 103680

llvm-svn: 103679

llvm-svn: 103677

lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668

Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.

llvm-svn: 103667

llvm-svn: 103665

llvm-svn: 103664

llvm-svn: 103663