Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.

llvm-svn: 98887

llvm-svn: 98869

No functional changes.

llvm-svn: 98860

There is a better way coming up.

llvm-svn: 98777

matches that of Firstcond[0] and E means otherwise.  The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing.  The disassembler also depends
on this arrangement.  This is similar to what's described in A2.5.2 ITSTATE.

Ran:

utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2

successfully.

llvm-svn: 98775

addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.

This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp.  It is used by disassembler as of now.

llvm-svn: 98774

llvm-svn: 98769

in svn r74988 but the format field was never widened.

llvm-svn: 98768

Remove it from ARMAddressingModes.h.

llvm-svn: 98751

instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98745

llvm-svn: 98692

optional register update argument, which is currently unused -- when we add
support for that, it can just be a separate operand.

llvm-svn: 98683

This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.

llvm-svn: 98679

llvm-svn: 98648

instructions for ld/st with writeback, the flag is completely redundant.

llvm-svn: 98643

llvm-svn: 98642

U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640

(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98637

This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.

llvm-svn: 98635

llvm-svn: 98596

Radar 7459078.

llvm-svn: 98586

section, remove the target-specific code that performs this.

llvm-svn: 98580

doesn't have a type constraint on the scalar because we don't have
an 'sAny' type.

llvm-svn: 98527

llvm-svn: 98503

llvm-svn: 98502

with an MCSymbol instead of an immediate.

llvm-svn: 98481

an MCSymbol.  Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID.  Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".

llvm-svn: 98463

instead of label ID's.  This cleans up and regularizes a bunch 
of code and makes way for future progress.

Unfortunately, this pointed out to me that JITDwarfEmitter.cpp
is largely copy and paste from DwarfException/MachineModuleInfo
and other places.  This is very sad and disturbing. :(

One major change here is that TidyLandingPads moved from being
called in DwarfException::BeginFunction to being called in
DwarfException::EndFunction.  There should not be any 
functionality change from doing this, but I'm not an EH expert.

llvm-svn: 98459

llvm-svn: 98451

and passing off ownership to AsmPrinter.  Now MachineModuleInfo
creates it and owns it by value.  This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code.  This also allows MachineFunction to 
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.

llvm-svn: 98450

llvm-svn: 98430

base register updating load/store-multiple instructions.

llvm-svn: 98427

writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409

mostly the same.

llvm-svn: 98402

llvm-svn: 98398

llvm-svn: 98395

llvm-svn: 98394

remove it.

llvm-svn: 98390

instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.

llvm-svn: 98285

for the NLP because the object it's pointing to may be internal to the file.

This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:

GCC_except_tbl:
  .long Lfoo-.

__ZTIA:  @ This is local
  ...

Lfoo:
  .long __ZTIA

LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.

llvm-svn: 98218