operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241

llvm-svn: 30112

llvm-svn: 29275

(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042

llvm-svn: 28984

llvm-svn: 28979

llvm-svn: 28864

llvm-svn: 28862

llvm-svn: 28860

llvm-svn: 28796

llvm-svn: 28594

llvm-svn: 28582

llvm-svn: 28578

llvm-svn: 28577

llvm-svn: 28565

llvm-svn: 28324

llvm-svn: 28131

movlps cannot be used (e.g. when load from m64 has multiple uses).

llvm-svn: 28089

llvm-svn: 27968

result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).

llvm-svn: 27965

a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).

llvm-svn: 27964

llvm-svn: 27960

scalar value.

e.g.
        _mm_set_epi32(0, a, 0, 0);
==>
	movd 4(%esp), %xmm0
	pshufd $69, %xmm0, %xmm0

        _mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
	movzbw 4(%esp), %ax
	movzwl %ax, %eax
	pxor %xmm0, %xmm0
	pinsrw $5, %eax, %xmm0

llvm-svn: 27923

llvm-svn: 27844

- Added more movhlps and movlhps patterns.

llvm-svn: 27842

llvm-svn: 27836

- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
  are preferred over shufps in most cases.

llvm-svn: 27835

- PINSRWrmi encoding bug.

llvm-svn: 27818

llvm-svn: 27816

llvm-svn: 27814

llvm-svn: 27813

llvm-svn: 27807

llvm-svn: 27782

llvm-svn: 27773

llvm-svn: 27762

llvm-svn: 27734

llvm-svn: 27733

llvm-svn: 27722

llvm-svn: 27721

llvm-svn: 27720