llvm-svn: 152207

ScheduleDAG has nothing to do with how the instructions are scheduled.

llvm-svn: 152206

ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152205

ScheduleDAG will not refer to the scheduled instruction sequence.

llvm-svn: 152204

llvm-svn: 152203

llvm-svn: 152178

Soon, ScheduleDAG will not refer to the BB.

llvm-svn: 152177

llvm-svn: 152176

llvm-svn: 152175

llvm-svn: 152174

llvm-svn: 152173

llvm-svn: 152172

as well as completely defined classes.

This fixes rdar://10956070

llvm-svn: 152171

Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).

llvm-svn: 152162

llvm-svn: 152153

llvm-svn: 152089

Make it possible for a target to mark FSUB as Expand.  This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.

llvm-svn: 152079

Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043

Patch by Sean Silva!

llvm-svn: 152042

llvm-svn: 152016

The first def of a virtual register cannot also read the register.
Assert on such bad machine code instead of trying to fix it.
TwoAddressInstructionPass should never create code like that.

llvm-svn: 152010

We are already setting <undef> flags, and that is good enough. The
<imp-def> operands don't mean anything any more.

llvm-svn: 152009

llvm-svn: 152001

llvm-svn: 151998

llvm-svn: 151996

llvm-svn: 151875

llvm-svn: 151874

to the string table for the function name, not the function name.

llvm-svn: 151873

The inline table needs to be constructed ahead of time so that it doesn't try to
create new strings while we're emitting everything.

This reverts commit a8ff9bccb399183cdd5f1c3cec2bda763664b4b0.

llvm-svn: 151864

fixups that are being used to determine section offsets. Reduces
the total number of fixups by 50% for a non-trivial testcase.

Part of rdar://10413936

llvm-svn: 151852

llvm-svn: 151849

Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.

Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".

llvm-svn: 151807

Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle.  Rewrite all operands in a bundle at
once.

Don't attempt and memory operand folding inside bundles.

llvm-svn: 151787

This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().

Also provide a const version. C++ is great for touch typing practice.

llvm-svn: 151782

While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.

llvm-svn: 151779

LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimization, making the lives of later passes easier.

llvm-svn: 151722

This function does more or less the same as
MI::readsWritesVirtualRegister(), but it supports bundles as well.

It also determines if any constraint requires reading and writing
operands to use the same register.  Most clients want to know.

Use the more modern MO.readsReg() instead of trying to sort out undefs
and partial redefines.  Stop supporting the extra full <imp-def> operand
as an alternative to <def,undef> sub-register defines.

llvm-svn: 151690

Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This eliminates the mystery bool constructor argument.

llvm-svn: 151684

methods are no longer needed now that LinearScan has gone away.

(Contains tweaks trivialSpillEverywhere to enable the removal of getNewVRegs).

llvm-svn: 151658

llvm-svn: 151645