FCAs. This is essential in order to promote allocas that are used in
struct returns by frontends like Clang. The FCA load would block the
rest of the pass from firing, resulting is significant regressions with
the bullet benchmark in the nightly test suite.

Thanks to Duncan for repeated discussions about how best to do this, and
to both him and Benjamin for review.

This appears to have blocked many places where the pass tries to fire,
and so I'm expect somewhat different results with this fix added.

As with the last big patch, I'm including a change to enable the SROA by
default *temporarily*. Ben is going to remove this as soon as the LNT
bots pick up the patch. I'm just trying to get a round of LNT numbers
from the stable machines in the lab.

NOTE: Four clang tests are expected to fail in the brief window where
this is enabled. Sorry for the noise!

llvm-svn: 164119

llvm-svn: 164117

More domain conversion; convert VFP VMOVS to NEON instructions in more cases - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not.

llvm-svn: 164114

Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.

llvm-svn: 164109

Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space.

llvm-svn: 164108

Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105

llvm-svn: 164101

llvm-svn: 164100

llvm-svn: 164099

llvm-svn: 164098

llvm-svn: 164097

llvm-svn: 164096

TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

llvm-svn: 164095

llvm-svn: 164094

llvm-svn: 164093

llvm-svn: 164092

Mark constructors, destructors, and operator new commented as 'do not implement' with LLVM_DELETED_FUNCTION instead.

llvm-svn: 164091

llvm-svn: 164090

aligned address. Based on patch by David Peixotto.

Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment
hints. rdar://12090772, rdar://12238782

llvm-svn: 164089

llvm-svn: 164088

llvm-svn: 164087

llvm-svn: 164086

and a conditional branch; also when removing dead cases from a switch.

llvm-svn: 164084

llvm-svn: 164078

Hanlde the case when we split the default edge if the default target has "icmp"
and unconditinal branch.

llvm-svn: 164076

llvm-svn: 164075

Add LIS::pruneValue() and extendToIndices(). These two functions are
used by the register coalescer when merging two live ranges requires
more than a trivial value mapping as supported by LiveInterval::join().

The pruneValue() function can remove the part of a value number that is
going to conflict in join(). Afterwards, extendToIndices can restore the
live range, using any new dominating value numbers and updating the SSA
form.

Use this complex value mapping to support merging a register into a
vector lane that has a conflicting value, but the clobbered lane is
undef.

llvm-svn: 164074

These extra operands are not needed by register allocators using
VirtRegRewriter, and RAFast don't need them any longer.

By omitting the <imp-def> operands, it becomes possible for the new
register coalescer to track which lanes are valid and which are undef.

llvm-svn: 164073

I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072

llvm-svn: 164071

llvm-svn: 164070

llvm-svn: 164068

llvm-svn: 164067

llvm-svn: 164066

llvm-svn: 164065

llvm-svn: 164064

llvm-svn: 164063

TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

llvm-svn: 164062

llvm-svn: 164061

llvm-svn: 164060