registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

llvm-svn: 134661

llvm-svn: 134281

llvm-svn: 134024

into XXXGenRegisterInfo.inc.

llvm-svn: 133922

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

that should be split out is the InstPrinter (if a target is mc'ized).
This change makes all the targets be consistent.

llvm-svn: 119056

llvm-svn: 94378

missing ones are libsupport, libsystem and libvmcore.  libvmcore is
currently blocked on bugpoint, which uses EH.  Once it stops using
EH, we can switch it off.

This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.

llvm-svn: 94164

 - Intended to match current TargetMachine implementations.

 - No facilities for linking these in yet.

llvm-svn: 75751

llvm-svn: 68383

llvm-svn: 61991

llvm-svn: 56486

llvm-svn: 45415

- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461