with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159

llvm-svn: 137831

llvm-svn: 137804

llvm-svn: 137515

llvm-svn: 136283

llvm-svn: 135537

Part of rdar://9643582

llvm-svn: 134084

llvm-svn: 133494

llvm-svn: 132777

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132444

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

been defined in MipsInstrFPU.td.

llvm-svn: 132076

llvm-svn: 132074

llvm-svn: 131012

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.

llvm-svn: 129594

llvm-svn: 128650

llvm-svn: 127034

llvm-svn: 127027

llvm-svn: 127003

llvm-svn: 123760

Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again

llvm-svn: 121164

Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.

llvm-svn: 117667

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786

changes before doing phi lowering for switches.

llvm-svn: 102809

const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635

MachineFunctionInfo subclasses.

llvm-svn: 101634

llvm-svn: 95506

llvm-svn: 95160

llvm-svn: 95130

Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626

llvm-svn: 85361

Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.

llvm-svn: 85281

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

llvm-svn: 80773

implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900