llvm-svn: 33971

llvm-svn: 33960

foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.

llvm-svn: 33958

llvm-svn: 33945

- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.

llvm-svn: 33944

llvm-svn: 33832

llvm-svn: 33831

- Add debugging info.

llvm-svn: 33811

llvm-svn: 33800

llvm-svn: 33795

llvm-svn: 33789

llvm-svn: 33788

llvm-svn: 33780

llvm-svn: 33778

llvm-svn: 33775

llvm-svn: 33773

llvm-svn: 33763

llvm-svn: 33762

llvm-svn: 33759

- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.

llvm-svn: 33753

to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744

llvm-svn: 33743

llvm-svn: 33741

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

two bytes padding.

llvm-svn: 33734

llvm-svn: 33733

llvm-svn: 33729

instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728

llvm-svn: 33727

llvm-svn: 33724

llvm-svn: 33723

change preferred alignment of short, byte, bool to 4.

llvm-svn: 33722

llvm-svn: 33721

llvm-svn: 33717

instruction field, adjust it for PC value (4 for thumb, 8 for arm).

llvm-svn: 33711

llvm-svn: 33707

llvm-svn: 33706

ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.

llvm-svn: 33703

llvm-svn: 33702

llvm-svn: 33699