saving and restoring them.

llvm-svn: 131745

No functionality enabled by default. Use -disable-iv-rewrite.
Extended IVUsers to keep track of the phi that represents the users' IV.
Added the WidenIV transform to replace a narrow IV with a wide IV
by doing a one-for-one replacement of IV users instead of expanding the
SCEV expressions. [sz]exts are removed and truncs are inserted.

llvm-svn: 131744

super.

llvm-svn: 131743

llvm-svn: 131740

llvm-svn: 131739

There's really nothing to implement. All this really does is swap to a
pseudo-section that later gets written to the unwind info struct. That
needs to be implemented in the object streamers.

llvm-svn: 131734

llvm-svn: 131730

llvm-svn: 131724

the phikill flag.

llvm-svn: 131717

llvm-svn: 131716

Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic

llvm-svn: 131714

llvm-svn: 131711

This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 

llvm-svn: 131710

llvm-svn: 131709

llvm-svn: 131708

similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!

llvm-svn: 131705

llvm-svn: 131689

foo:
bar = foo
.quad bar

Avoid producing it. Fixes PR9951.

llvm-svn: 131687

* Remove unnecessary arguments now that ForceExpAbs is a method.
* Use ForceExpAbs in EmitAbsValue.

llvm-svn: 131683

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

llvm-svn: 131679

the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

llvm-svn: 131677

Fix up this test to use explicit triples (Win64 passes a different number of arguments in registers).

llvm-svn: 131676

text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674

Reapply r131605. This time with a fix, which is to use NoFolder.

llvm-svn: 131673

Fixes PR9934.

We really need to start tblgening the relocation info :-(

llvm-svn: 131669

llvm-svn: 131668

I had to change the API slightly to avoid overloading issues.

llvm-svn: 131666

llvm-svn: 131665

llvm-svn: 131664

llvm-svn: 131663

llvm-svn: 131660

llvm-svn: 131659

llvm-svn: 131657

Introduce -fatal-assembler-warnings for the obvious purpose

llvm-svn: 131655

llvm-svn: 131654

llvm-svn: 131653

ours compatible with GAS.

In retrospect, I should have emailed binutils about this earlier. Thanks to
Kai Tietz for pointing out that GAS already had SEH directives.

llvm-svn: 131652

llvm-svn: 131649

llvm-svn: 131644