- Added ability to emit cross class register copies to the BBRU scheduler.
- More aggressive backtracking.

llvm-svn: 42375

llvm-svn: 42373

- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372

Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.

llvm-svn: 42371

llvm-svn: 42368

instruction creation. No support yet for instruction introspection.

Also eliminated allocas from the Ocaml bindings for portability,
and avoided unnecessary casts.

llvm-svn: 42367

llvm-svn: 42359

llvm-svn: 42348

llvm-svn: 42347

Tested with "make check"!

llvm-svn: 42346

llvm-svn: 42345

llvm-svn: 42335

llvm-svn: 42333

llvm-svn: 42332

llvm-svn: 42329

cases with undefined behavior.

llvm-svn: 42328

llvm-svn: 42323

llvm-svn: 42322

llvm-svn: 42316

llvm-svn: 42314

llvm-svn: 42313

llvm-svn: 42312

This fixes PR714.

llvm-svn: 42309

both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.

llvm-svn: 42308

llvm-svn: 42306

doh.. 

llvm-svn: 42300

for (i=A; i<N; i++) {
  if (i < X && i > Y)
    do_something();
}

is transformed into

U=min(N,X); L=max(A,Y);
for (i=L;i<U;i++)
  do_somethihg();                            

llvm-svn: 42299

of zero, infinity, and NaNs.

llvm-svn: 42298

the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.

llvm-svn: 42297

llvm-svn: 42294

Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285

Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.

llvm-svn: 42284

llvm-svn: 42283

llvm-svn: 42282

have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)

llvm-svn: 42281

llvm-svn: 42280

llvm-svn: 42279

instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.

llvm-svn: 42278

such as will happen when .loc directives are used.

llvm-svn: 42277

consistency with the other currently empty sections.

llvm-svn: 42276