llvm-svn: 57750

llvm-svn: 57749

and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.

llvm-svn: 57747

No functionality change.

llvm-svn: 57746

llvm-svn: 57745

llvm-svn: 57744

llvm-svn: 57743

llvm-svn: 57742

Hack: have BasicStore::getLValueElement return the "Base" lvalue.  This restores null dereference checking with array accesses.

BasicStore::RemoveDeadBindings: handle regions besides VarRegions (we now have FieldRegions).

llvm-svn: 57741

When conjuring symbols to recover path-sensitivity, don't conjure symbols that represent an entire struct.  We need to implement struct temporaries as an actual "region", and then bind symbols to the FieldRegion of those temporaries.

llvm-svn: 57739

 - Shouldn't assume predefined expr is a function printing one.
 - Uses CGM functionality to cache function names per module.

llvm-svn: 57737

(first) global holding the string.
 - No functionality change.

llvm-svn: 57736

llvm-svn: 57735

llvm-svn: 57734

llvm-svn: 57733

llvm-svn: 57731

Enhance "Assumption" logic in BasicConstraintManager when reasoning about regions and symbolic regions.  When assuming whether or not a location is non-null, walk up the region hierarchy until we hit a symbolic region (and test it for null).  This may not be the end all solution, as the notion of what a "symbolic region" is really belongs in the specific subclass of StoreManager.

llvm-svn: 57730

ISD condition opcodes into helper functions.

llvm-svn: 57726

llvm-svn: 57724

Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file.

llvm-svn: 57723

Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.

TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722

assert.

llvm-svn: 57721

Patch by Lang Hames!

llvm-svn: 57720

Fixed an elusive caching bug in ExplodedGraph construction when a PostStmtKind was used instead of a PostStoreKind.

llvm-svn: 57719

llvm-svn: 57718

- Added new region "SymbolicRegion", which maps symbol values to the region domain.
- Enhanced BasicStore::getFieldLValue() to return a FieldRegion (using SymbolicRegion)
- Added some utility methods to GRState for fetch svals from the store.
- Fixed regression in CheckNSError (we weren't getting the value bound to the parameter)

llvm-svn: 57717

llvm-svn: 57716

llvm-svn: 57715

have an unreachable block in a function. This was triggering the assert. This is
a horrid hack to cover this up.

Oh! for a good debug info architecture!

llvm-svn: 57714

touches memory and need an associated MemOperand

llvm-svn: 57712

ISD condition opcodes into helper functions.

llvm-svn: 57710

llvm-svn: 57709

in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.

llvm-svn: 57704

that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.

llvm-svn: 57699

llvm-svn: 57696

llvm-svn: 57695

other than why it was xfailed.

llvm-svn: 57694

"Implement" GRExprEngine::VisitLValue for ObjCPropertyRefExpr.  This is only a bandid; we need to properly handle properties by using locv/nonloc objects and specially handling property assignments in the transfer function for BinaryOperator.

llvm-svn: 57693

Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.

llvm-svn: 57692