llvm-svn: 120298

llvm-svn: 120235

llvm-svn: 120229

llvm-svn: 120228

llvm-svn: 120146

llvm-svn: 119990

This currently only catches the most basic case, a two-case switch, but can be
extended later.

llvm-svn: 119964

llvm-svn: 119904

llvm-svn: 119903

so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901

Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.

llvm-svn: 119898

llvm-svn: 119896

llvm-svn: 119895

llvm-svn: 119875

DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.

llvm-svn: 119819

Patch by Krister Wombell!

llvm-svn: 119791

MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.

This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.

llvm-svn: 119777

llvm-svn: 119754

llvm-svn: 119740

not anyext(select).  Spotted by Frits van Bommel.

llvm-svn: 119739

if the extension types were not the same.  The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext).  Reported
and diagnosed by Sebastien Deldon.

llvm-svn: 119728

llvm-svn: 119717

llvm-svn: 119716

llvm-svn: 119712

simple form of INITIALIZE_PASS.

llvm-svn: 119707

and testing is easier.  A good example is the unknown-location.ll test that
now can just look for ".loc 1 0 0".  We also don't use a DW_LNE_set_address for
every address change anymore.

llvm-svn: 119613

memset; we may need it to decide between MOVAPS and MOVUPS
later.  Adjust a test that was looking for wrong code.
PR 3866 / 8675131.

llvm-svn: 119605

llvm-svn: 119590

and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548

SrcMgrDiagHandler, we can improve clang diagnostics for inline asm:
instead of reporting them on a source line of the original line,
we can report it on the correct line wherever the string literal came
from. For something like this:

void foo() {
  asm("push %rax\n"
      ".code32\n");
}

we used to get this: (note that the line in t.c isn't helpful)

t.c:4:7: error: warning: ignoring directive for now
  asm("push %rax\n"
      ^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^

now we get:

t.c:5:8: error: warning: ignoring directive for now
      ".code32\n"
       ^
<inline asm>:2:1: note: instantiated into assembly here
.code32
^

Note that we're pointing to line 5 properly now.

llvm-svn: 119488

cookie argument to the SourceMgr diagnostic stuff.  This cleanly separates
LLVMContext's inlineasm handler from the sourcemgr error handling 
definition, increasing type safety and cleaning things up.

llvm-svn: 119486

the cookie argument to setDiagHandler

llvm-svn: 119483

llvm-svn: 119482

operands in a variadic instruction.

llvm-svn: 119446

llvm-svn: 119386

llvm-svn: 119385

easier to debug, and to avoid complications when the CFG changes
in the middle of the instruction selection process.

llvm-svn: 119382

Always spill the full representative register at any point where any subregister
is live.

This fixes PR8620 which caused the old logic to get confused and not spill
anything at all.

The fundamental problem here is that the coalescer is too aggressive about
physical register coalescing. It sometimes makes it impossible to allocate
registers without these emergency spills.

llvm-svn: 119375

llvm-svn: 119374

(and likely) wrong about anyhow.

llvm-svn: 119320