Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.

llvm-svn: 35658

Use local variable names that match the function parameter name that it
is passed to so the code is more clear, to wit: is_bytecode -> is_native

llvm-svn: 35656

llvm-svn: 35655

Implement file tests for both LinkInLibrary and LinkInFile to determine if
the file is native. Don't generate warnings if the file is native.

llvm-svn: 35653

Adjust useage of sys::Path::FileType for new enumerator names.

llvm-svn: 35651

Implement recognition of COFF, ELF and Mach-O object/shared lib files.

llvm-svn: 35650

llvm-svn: 35644

initialized this way, they do not do a malloc to allocate their buckets.

llvm-svn: 35642

llvm-svn: 35640

llvm-svn: 35639

llvm-svn: 35638

llvm-svn: 35637

llvm-svn: 35635

llvm-svn: 35634

some constant exprs to apints).

Thanks to Anton for tracking down a small testcase that triggered this!

llvm-svn: 35633

llvm-svn: 35632

llvm-svn: 35627

ldecod now passes.

llvm-svn: 35626

LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.

llvm-svn: 35625

as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.

llvm-svn: 35624

"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."

llvm-svn: 35623

F1-F10. This affects only ELF, not MachO.

llvm-svn: 35622

llvm-svn: 35620

llvm-svn: 35619

llvm-svn: 35618

llvm-svn: 35617

llvm-svn: 35616

llvm-svn: 35615

llvm-svn: 35614

llvm-svn: 35612

CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609

llvm-svn: 35607

2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605

llvm-svn: 35602

to be folded into non-store instructions.

llvm-svn: 35601

llvm-svn: 35600

llvm-svn: 35598

2. Use cheaper APInt methods.

llvm-svn: 35594

llvm-svn: 35593

target hook.  This allows us to codegen a loop as:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0, +r3, lsl #2]
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

instead of:

LBB1_1: @cond_next
        mov r2, #0
        str r2, [r0], #+4
        add r3, r3, #1
        cmn r3, #1
        bne LBB1_1      @cond_next

This looks the same, but has one fewer induction variable (and therefore,
one fewer register) live in the loop.

llvm-svn: 35592