llvm-svn: 158575

Calling checkRegMaskInterference(VirtReg) checks if VirtReg crosses any
regmask operands, regardless of the registers they clobber.

llvm-svn: 158563

iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.

llvm-svn: 158560

This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi

For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.

rdar: 11633193
llvm-svn: 158551

llvm-svn: 158543

For non-address users, Base and Scaled registers are not specially
associated to fit an address mode, so SCEVExpander should apply normal
expansion rules. Otherwise we may sink computation into inner loops
that have already been optimized.

llvm-svn: 158537

llvm-svn: 158536

llvm-svn: 158535

Allow SROA to split up an array of vectors into multiple vectors, even when the vectors are dynamically indexed

llvm-svn: 158529

linkonce linkage. For example, it is not valid to add unnamed_addr.

This also fixes a crash in g++.dg/opt/static5.C.

llvm-svn: 158528

This probably mostly shows up in bugpoint-generated code.

llvm-svn: 158527

We only do very limited physreg coalescing now, but we still merge
virtual registers into reserved registers.

llvm-svn: 158526

Patch extracted from a larger one by the PaX team. I added the testcases
and tightened error handling a bit.

llvm-svn: 158523

example degenerate phi nodes and binops that use themselves in unreachable code.
Thanks to Charles Davis for the testcase that uncovered this can of worms.

llvm-svn: 158508

llvm-svn: 158497

llvm-svn: 158485

llvm-svn: 158484

Recommit r158407: Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access.  Now with additional fix and test for indexing into a vector inside a struct

llvm-svn: 158479

globaldce. Globaldce was already removing linkonce globals, but globalopt was
not.

llvm-svn: 158476

Can someone with more knowledge of this please look at other entries
to see if others need moved.

llvm-svn: 158474

llvm-svn: 158471

being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470

the last instruction of a basic block.

llvm-svn: 158468

llvm-svn: 158467

This reverts commit 12c1f86ffa731e2952c80d2cc577000c96b8962c.

llvm-svn: 158462

llvm-svn: 158461

Recommit r158407: Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access.  Now with additional fix and test for indexing into a vector inside a struct

llvm-svn: 158454

llvm-svn: 158446

llvm-svn: 158445

llvm-svn: 158443

uno && ueq was converted to ueq, it should be converted to uno.

llvm-svn: 158441

llvm-svn: 158437

llvm-svn: 158436

llvm-svn: 158434

llvm-svn: 158433

as a scratch register when they are expanded to long branches.

llvm-svn: 158432

to load an immediate that does not fit into 16-bit. 

llvm-svn: 158431

to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size. 

llvm-svn: 158430

compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.

llvm-svn: 158429

Long-branches need access to the global base register to get the destination
address.

llvm-svn: 158428