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  1. Jun 14, 2009
  2. Jun 13, 2009
    • Evan Cheng's avatar
      Add a ARM specific pre-allocation pass that re-schedule loads / stores from · 185c9ef0
      Evan Cheng authored
      consecutive addresses togther. This makes it easier for the post-allocation pass
      to form ldm / stm.
      
      This is step 1. We are still missing a lot of ldm / stm opportunities because
      of register allocation are not done in the desired order. More enhancements
      coming.
      
      llvm-svn: 73291
      185c9ef0
    • Devang Patel's avatar
      llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in... · 64e6529e
      Devang Patel authored
      llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function.  If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available.  LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. 
      Apply defensive patch to preserve at least one lexical scope till the end of function.
      
      llvm-svn: 73282
      64e6529e
    • Owen Anderson's avatar
      Improve style. · c59a7cb8
      Owen Anderson authored
      llvm-svn: 73258
      c59a7cb8
  3. Jun 12, 2009
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