- Jun 14, 2009
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Bruno Cardoso Lopes authored
Introduce new BinaryObject (blob) class, ELF Writer modified to use it. BinaryObject.h by Aaron Gray llvm-svn: 73333
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- Jun 13, 2009
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Evan Cheng authored
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
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Devang Patel authored
llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics. Apply defensive patch to preserve at least one lexical scope till the end of function. llvm-svn: 73282
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Owen Anderson authored
llvm-svn: 73258
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- Jun 12, 2009
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Owen Anderson authored
llvm-svn: 73257
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Owen Anderson authored
llvm-svn: 73256
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Evan Cheng authored
If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register. llvm-svn: 73255
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Devang Patel authored
llvm-svn: 73244
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- Jun 11, 2009
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Bruno Cardoso Lopes authored
Emission for globals, using the correct data sections Function alignment can be computed for each target using TargetELFWriterInfo Some small fixes llvm-svn: 73201
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Oscar Fuentes authored
llvm-svn: 73174
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- Jun 10, 2009
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Sanjiv Gupta authored
llvm-svn: 73156
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- Jun 09, 2009
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Owen Anderson authored
Add the beginnings of an implementatation of lazy liveness analysis, based on "Fast Liveness Checking for SSA-form Programs" by Boissinot, et al. This is still very early, hasn't been tested, and is not yet well documented. More to come soon. llvm-svn: 73141
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- Jun 07, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 73040
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Bruno Cardoso Lopes authored
llvm-svn: 73039
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Bruno Cardoso Lopes authored
relocation sections. llvm-svn: 73038
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Eli Friedman authored
converting from an MMX vector to an i64. llvm-svn: 73024
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Eli Friedman authored
on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. llvm-svn: 73012
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- Jun 06, 2009
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Eli Friedman authored
types. llvm-svn: 72993
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Eli Friedman authored
llvm-svn: 72992
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Bruno Cardoso Lopes authored
llvm-svn: 72982
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Eli Friedman authored
integer type to be consistent with normal operation legalization. No visible change because nothing is actually using this at the moment. llvm-svn: 72980
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- Jun 05, 2009
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Devang Patel authored
Update code generator to use this attribute and remove NoImplicitFloat target option. Update llc to set this attribute when -no-implicit-float command line option is used. llvm-svn: 72959
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Nate Begeman authored
build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret llvm-svn: 72957
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Dan Gohman authored
llvm-svn: 72948
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Sanjiv Gupta authored
llvm-svn: 72941
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Bruno Cardoso Lopes authored
MachO Writer. This will change with the arrival of ObjectCodeEmitter and BinaryObject llvm-svn: 72906
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Dan Gohman authored
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
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- Jun 04, 2009
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Dale Johannesen authored
using Promote which won't work because i64 isn't a legal type. It's easy enough to use Custom, but then we have the problem that when the type legalizer is promoting FP_TO_UINT->i16, it has no way of telling it should prefer FP_TO_SINT->i32 to FP_TO_UINT->i32. I have uncomfortably hacked this by making the type legalizer choose FP_TO_SINT when both are Custom. This fixes several regressions in the testsuite. llvm-svn: 72891
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Evan Cheng authored
RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. llvm-svn: 72890
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Evan Cheng authored
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. llvm-svn: 72889
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Lang Hames authored
llvm-svn: 72880
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Dan Gohman authored
instcombine doesn't know when it's safe. To partially compensate for this, introduce new code to do this transformation in dagcombine, which can use UnsafeFPMath. llvm-svn: 72872
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Dan Gohman authored
llvm-svn: 72870
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Dan Gohman authored
llvm-svn: 72828
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Lang Hames authored
llvm-svn: 72825
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- Jun 03, 2009
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Bruno Cardoso Lopes authored
llvm-svn: 72785
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Oscar Fuentes authored
llvm-svn: 72775
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Evan Cheng authored
Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well. llvm-svn: 72758
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Evan Cheng authored
If there is a def of a super-register followed by a use of a sub-register, do *not* add an implicit def of the sub-register. e.g. EAX = ..., AX<imp-def> ... = AX This creates a double-def. Apparently this used to be necessary but is no longer needed. Thanks to Anton for pointing this out. Anton, I cannot create a test case without your uncommitted ARM patches. Please check in a test case for me. llvm-svn: 72755
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Bruno Cardoso Lopes authored
one new .cpp file, in preparation for merging in the Direct Object Emission changes we're working on. No functional changes. Fixed coding style issues on the original patch. Patch by Aaron Gray llvm-svn: 72754
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