The CELL backend cannot select patterns for  vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.

llvm-svn: 142081

llvm-svn: 142080

llvm-svn: 142073

It really doesn't, but when r141929 removed the hasSideEffects flag from
this instruction, it caused miscompilations.  I am guessing that it got
moved across a stack pointer update.

Also clear isRematerializable after checking that this instruction is
in fact never rematerialized in the nightly test suite.

llvm-svn: 142030

rdar://10288916 is tracking this fix.

In the past, instcombine and other passes were promoting alloca alignment past
the natural alignment, resulting in dynamic stack realignment.  Lang's work now
prevents this from happening (LLVM commit r141599).  Now that this really 
shouldn't happen report a fatal error rather than silently generate bad code.

llvm-svn: 142028

llvm-svn: 142027

llvm-svn: 142022

llvm-svn: 142021

The callee-saved registers cannot be live across an invoke call because the
control flow may continue along the exceptional edge. When this happens, all of
the callee-saved registers are no longer valid.

llvm-svn: 142018

    assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000

llvm-svn: 141988

llvm-svn: 141981

llvm-svn: 141978

llvm-svn: 141972

llvm-svn: 141959

llvm-svn: 141947

Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.

llvm-svn: 141939

Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141938

Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141937

Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141936

Patch by Jack Carter at Mips. 

llvm-svn: 141934

Patch by Jack Carter at Mips. 

llvm-svn: 141932

TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929

TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

llvm-svn: 141924

llvm-svn: 141914

llvm-svn: 141912

llvm-svn: 141909

llvm-svn: 141903

llvm-svn: 141874

Not having it confused assembly printing of jumptables.

llvm-svn: 141862

release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859

http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857

Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.

llvm-svn: 141856

Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.

llvm-svn: 141854

llvm-svn: 141853

The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819

llvm-svn: 141811

llvm-svn: 141794

llvm-svn: 141786

llvm-svn: 141781