an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.

llvm-svn: 4781

llvm-svn: 4780

    wasn't an optimization and it was causing lots of bugs.

llvm-svn: 4779

llvm-svn: 4778

and it causes obscure bugs to show up in passes.

llvm-svn: 4777

uncovered a bug where registers were not being put in a map if they were not
found...

llvm-svn: 4776

llvm-svn: 4775

imply types of SSA Registers. This is on a per-function basis, so the
MachineFunction contains the SSARegMap, and has accessor functions to it.

llvm-svn: 4774

belong to different register classes easier.

llvm-svn: 4773

llvm-svn: 4772

llvm-svn: 4771

llvm-svn: 4770

llvm-svn: 4769

llvm-svn: 4768

llvm-svn: 4767

llvm-svn: 4766

llvm-svn: 4765

llvm-svn: 4764

llvm-svn: 4763

llvm-svn: 4762

llvm-svn: 4761

llvm-svn: 4760

llvm-svn: 4759

llvm-svn: 4758

llvm-svn: 4757

llvm-svn: 4756

lib/Target/X86/InstSelectSimple.cpp: Add a little something to
 visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8

llvm-svn: 4755

llvm-svn: 4754

Add (currently disabled) faciility to try to filter out pool allocation overhead from memory usage stats

llvm-svn: 4753

llvm-svn: 4752

llvm-svn: 4751

llvm-svn: 4750

Add structure padding optimizations

llvm-svn: 4749

llvm-svn: 4748

llvm-svn: 4747

llvm-svn: 4746

llvm-svn: 4745

llvm-svn: 4744

Start trying to print instructions more correctly.  For now we also print out the opcode for each instruction as well.

llvm-svn: 4743

llvm-svn: 4742