llvm-svn: 7437

ordinary (primitive) types since ConstantExprs may be of primitive type!

llvm-svn: 7418

it's currently not used.

llvm-svn: 7416

have changed.

llvm-svn: 7414

llvm-svn: 7404

* Enabled STXFSR instructions

llvm-svn: 7400

llvm-svn: 7399

in ConvertConstantToIntType.

llvm-svn: 7395

llvm-svn: 7394

which were wrong (particularly, '\a' for '\007').

llvm-svn: 7393

that depends on machine register size.
Moved insertCallerSavingCode() to PhyRegAlloc and
moved isRegVolatile and modifiedByCall to TargetRegInfo: they are all
machine independent.  Remove several dead functions.

llvm-svn: 7392

immed. field.  Moved insertCallerSavingCode() to PhyRegAlloc: it is
now machine independent.  Remove all uses of PhyRegAlloc.

llvm-svn: 7391

  instead of assert()ing
* Fixed a nasty bug where '07' was used instead of register 'o7'

llvm-svn: 7382

llvm-svn: 7357

llvm-svn: 7343

    Single and FP double reg types (which share the same reg class).
    Now all methods marking/finding unused regs consider the regType
    within the reg class, and SparcFloatRegClass specializes this code.
(2) Remove machine-specific regalloc. methods that are no longer needed.
    In particular, arguments and return value from a call do not need
    machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
    overloading when an include file is omitted.

llvm-svn: 7334

   causing a nasty array bound error later.
2. Fix silly typo causing logical shift of unsigned long to use
   SRL instead of SRLX.

llvm-svn: 7330

llvm-svn: 7253

whether the constant is signed or unsigned, then casting

llvm-svn: 7252

llvm-svn: 7217

llvm-svn: 7208

now works in instructions which require a 2-bit or 3-bit INTcc code.

Incidentally, that means that the representation of INTcc registers is now the
same in both integer and FP instructions. Thus, code became much simpler and
cleaner.

llvm-svn: 7185

no change in functionality.

llvm-svn: 7184

llvm-svn: 7182

llvm-svn: 7181

allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).

Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.

llvm-svn: 7178

* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
  broken (because regTypes are broken)

llvm-svn: 7175

llvm-svn: 7173

(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.

(2) Conditional move instructions must distinguish signed and unsigned
    condition codes, e.g., MOVLE vs. MOVLEU.

(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
    which produces a valid-looking instruction with bogus registers!

(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
    add 2^k-1 before shifting, not add 1 after shifting.  Sadly, these
    are the same when k=0 so our poor test case worked fine.

(5) Casting between signed and unsigned values was not correct:
    completely reimplemented.

(6) Zero-extension on unsigned values was bogus: I was only doing the
    SRL and not the SLLX before it.  Don't know WHAT I was thinking!

(7) And the most important class of changes: Sign-extensions on signed values.
    Signed values are not sign-extended after ordinary operations,
    so they must be sign-extended before the following cases:
	-- passing to an external or unknown function
	-- returning from a function
	-- using as operand 2 of DIV or REM
	-- using as either operand of condition-code setting operation
           (currently only SUBCC), with smaller than 32-bit operands


Also, a couple of improvements:

(1) Fold cast-to-bool into Not(bool).  Need to do this for And, Or, XOR also.

(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
    if the constant is 0.  This was only being done for branch-on-SetCC-Const
    when the branch is folded with the SetCC-Const.

llvm-svn: 7159

llvm-svn: 7158

boolean operations: AND, OR, XOR.

llvm-svn: 7157

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7151

llvm-svn: 7120

some comments.

llvm-svn: 7119

llvm-svn: 7114

llvm-svn: 7113

integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.

llvm-svn: 7111

llvm-svn: 7109

correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.

This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.

llvm-svn: 7103

  the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
  actually assigned into the right portion of the instruction.

llvm-svn: 7074