preallocated.  While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.

llvm-svn: 6467

globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.

llvm-svn: 6466

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

llvm-svn: 6464

llvm-svn: 6463

llvm-svn: 6462

Created new classes from which instructions inherit their ordering of fields.

llvm-svn: 6461

* Fixed page numbers referring to the Sparc manual

llvm-svn: 6460

llvm-svn: 6459

llvm-svn: 6457

"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456

Fixed BasicBlock patching by supplying correct type for the displacement.

llvm-svn: 6453

llvm-svn: 6452

llvm-svn: 6451

* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers

llvm-svn: 6449

sections of instructions.

llvm-svn: 6448

For one, converting register numbers based on class in the code emitter.

llvm-svn: 6447

Code beautification for the rest of the code: changed layout to match the rest
of the code base.

llvm-svn: 6446

llvm-svn: 6444

broken up into their elements.  Too many programs break because of this.

llvm-svn: 6440

llvm-svn: 6439

behavior is technically undefined

llvm-svn: 6438

instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

llvm-svn: 6437

internal phi nodes, and returns a new vector of basic blocks.

llvm-svn: 6431

SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.

llvm-svn: 6429

llvm-svn: 6428

llvm-svn: 6425

llvm-svn: 6424

llvm-svn: 6423

llvm-svn: 6420

llvm-svn: 6415

llvm-svn: 6411

has their path set up by this point.

llvm-svn: 6410

llvm-svn: 6403

llvm-svn: 6397

* Make the function inliner _significantly_ smarter.  :)

llvm-svn: 6396

exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.

Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.

llvm-svn: 6392

llvm-svn: 6390

Also, added a rule to delete the generated .inc file on `make clean'.

llvm-svn: 6389

* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr

llvm-svn: 6388