- Dec 20, 2010
-
-
Chris Lattner authored
doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret llvm-svn: 122217
-
Mon P Wang authored
llvm-svn: 122216
-
Mon P Wang authored
llvm-svn: 122215
-
Chris Lattner authored
llvm-svn: 122214
-
Chris Lattner authored
their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
-
Chris Lattner authored
llvm-svn: 122212
-
Chris Lattner authored
Imagine we see: EFLAGS = inst1 EFLAGS = inst2 FLAGS gpr = inst3 EFLAGS Previously, we would refuse to schedule inst2 because it clobbers the EFLAGS of the predecessor. However, it also uses the EFLAGS of the predecessor, so it is safe to emit. SDep edges ensure that the right order happens already anyway. This fixes 2 testsuite crashes with the X86 patch I'm going to commit next. llvm-svn: 122211
-
Mon P Wang authored
llvm-svn: 122210
-
Chris Lattner authored
llvm-svn: 122209
-
Chris Lattner authored
llvm-svn: 122208
-
Cameron Zwarich authored
PR8822. llvm-svn: 122207
-
Mon P Wang authored
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
-
Cameron Zwarich authored
half of PR8813. llvm-svn: 122205
-
Chris Lattner authored
llvm-svn: 122204
-
- Dec 19, 2010
-
-
Bruno Cardoso Lopes authored
llvm-svn: 122203
-
Cameron Zwarich authored
ConnectedVNInfoEqClasses::Classify(). llvm-svn: 122202
-
Chris Lattner authored
consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
-
Greg Clayton authored
table offset where the offset is within a section. Increased the section offset for line table entries to be 32 bits (from 24 bits), giving each section a 4G offset, and increased the section index to 32 bits (from 8 bits). llvm-svn: 122200
-
Cameron Zwarich authored
llvm-svn: 122199
-
Greg Clayton authored
llvm-svn: 122198
-
Cameron Zwarich authored
llvm-svn: 122197
-
Chris Lattner authored
going through the CSE maps to get it. llvm-svn: 122196
-
Nick Lewycky authored
llvm-svn: 122195
-
Nick Lewycky authored
llvm-svn: 122194
-
Nick Lewycky authored
llvm-svn: 122193
-
Nick Lewycky authored
headers provide symbols outside namespace std and the LLVM coding standards state that we should prefix all of them. llvm-svn: 122192
-
Chris Lattner authored
enough to teach it that ADDE(0,0) is known 0 except the low bit, for example. llvm-svn: 122191
-
Chris Lattner authored
llvm-svn: 122190
-
Chris Lattner authored
we don't need -disable-mmx anymore. llvm-svn: 122189
-
Chris Lattner authored
tests don't need -disable-mmx. llvm-svn: 122188
-
Chris Lattner authored
llvm-svn: 122187
-
Chris Lattner authored
generate them. Now we compile: define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp { entry: %0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b) %cmp = extractvalue %0 %0, 1 br i1 %cmp, label %if.then, label %if.end into: _X: ## @X ## BB#0: ## %entry subl $12, %esp movb 16(%esp), %al addb 20(%esp), %al jo LBB0_2 Before we were generating: _X: ## @X ## BB#0: ## %entry pushl %ebp movl %esp, %ebp subl $8, %esp movb 12(%ebp), %al testb %al, %al setge %cl movb 8(%ebp), %dl testb %dl, %dl setge %ah cmpb %cl, %ah sete %cl addb %al, %dl testb %dl, %dl setge %al cmpb %al, %ah setne %al andb %cl, %al testb %al, %al jne LBB0_2 llvm-svn: 122186
-
Chris Lattner authored
llvm-svn: 122185
-
Wesley Peck authored
2. Add attibutes "interrupt_handler" and "save_volatiles" for the Microblaze target. llvm-svn: 122184
-
Chris Lattner authored
llvm-svn: 122183
-
Chris Lattner authored
This resolves a README entry and technically resolves PR4916, but we still get poor code for the testcase in that PR because GVN isn't CSE'ing uadd with add, filed as PR8817. Previously we got: _test7: ## @test7 addq %rsi, %rdi cmpq %rdi, %rsi movl $42, %eax cmovaq %rsi, %rax ret Now we get: _test7: ## @test7 addq %rsi, %rdi movl $42, %eax cmovbq %rsi, %rax ret llvm-svn: 122182
-
Chris Lattner authored
result is dead. This is required for my next patch to not regress the testsuite. llvm-svn: 122181
-
Chris Lattner authored
llvm-svn: 122180
-
Chris Lattner authored
the old thing end up on the instcombine worklist. Not doing this can cause an extra top-level iteration of instcombine, burning compile time. llvm-svn: 122179
-
Chris Lattner authored
sadd formed is half the size of the original type. We can now compile this into a sadd.i8: unsigned char X(char a, char b) { int res = a+b; if ((unsigned )(res+128) > 255U) abort(); return res; } llvm-svn: 122178
-