Commits · 46de41330ca51f665f422dbcb7ea48076cdc345f · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Nov 06, 2016
- [AVX-512] Remove intrinsics for 128/256-bit masked variable shift. Instead... · 46de4133
  Craig Topper authored Nov 06, 2016
  46de4133
- [AVX-512] Remove intrinsics for 128/256-bit masked shift by immediate. Instead... · af9b3fe7
  Craig Topper authored Nov 06, 2016
  af9b3fe7
- [AVX-512] Remove intrinsics for 128/256-bit masked shift by single element in... · c9467ed3
  Craig Topper authored Nov 06, 2016
  c9467ed3
- [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsElementInsertion. NFCI · b3ad5f7e
  Simon Pilgrim authored Nov 06, 2016
  b3ad5f7e
- [AVX-512] Add missing EVEX version of pattern for (v2f64 (extloadv2f32 addr:)) -> VCVTPS2PDZ128rm · 5471fc29
  Craig Topper authored Nov 06, 2016
  5471fc29
- [AVX-512] Lower AVX cvtpd2ps intrinsic to ISD::FP_ROUND so it can use EVEX... · 1162857e
  Craig Topper authored Nov 06, 2016
  1162857e
- [AVX-512] Lower SSE/AVX cvtdq2ps intrinsics directly to ISD::SINT_TO_FP so... · 9a4a3af5
  Craig Topper authored Nov 06, 2016
  9a4a3af5
Nov 05, 2016
- [Hexagon] Relocate pattern-related bits to proper places · 2839b29f
  Krzysztof Parzyszek authored Nov 05, 2016
  2839b29f
- [Hexagon] Round 1 of selection pattern simplifications · 4b4012a5
  Krzysztof Parzyszek authored Nov 05, 2016
  4b4012a5
- [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsBlend. NFCI · 4a9f2104
  Simon Pilgrim authored Nov 05, 2016
  4a9f2104
- [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsZeroOrAnyExtend. NFCI · 72517469
  Simon Pilgrim authored Nov 05, 2016
  72517469
- [X86][SSE] Reuse zeroable element mask in SSE4A EXTRQ/INSERTQ vector shuffle lowering. NFCI · 9f0afc6a
  Simon Pilgrim authored Nov 05, 2016
  9f0afc6a
- [X86][SSE] Reuse zeroable element mask in PSHUFB vector shuffle lowering. NFCI · 3cae2196
  Simon Pilgrim authored Nov 05, 2016
  3cae2196
- [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsInsertPS. NFCI · 64a592d0
  Simon Pilgrim authored Nov 05, 2016
  64a592d0
- [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsBitMask. NFCI · 009befbd
  Simon Pilgrim authored Nov 05, 2016
  009befbd
- [X86][SSE] Reuse zeroable element mask instead of regenerating it. NFCI · 1af0fc11
  Simon Pilgrim authored Nov 05, 2016
  1af0fc11
- [Hexagon] Split all selection patterns into a separate file · a8d63dc2
  Krzysztof Parzyszek authored Nov 05, 2016
  a8d63dc2
- Strip trailing whitespace. NFCI. · 1b4e1ac9
  Simon Pilgrim authored Nov 05, 2016
  1b4e1ac9
Nov 04, 2016
- [Hexagon] Account for <def,read-undef> when validating moves for predication · b7eb7fc8
  Krzysztof Parzyszek authored Nov 04, 2016
  b7eb7fc8
- [X86] Broadcast from memory intructions aren't unfoldable · 85bc64c7
  Zvi Rackover authored Nov 04, 2016
  85bc64c7
- Revert "AMDGPU: Add VI i16 support" · 2d2d33f1
  Tom Stellard authored Nov 04, 2016
  2d2d33f1
- X86: Move a non-null assert to before the pointer is dereferenced · 2c2c6ac7
  Justin Bogner authored Nov 03, 2016
  2c2c6ac7
- Sink all of the code relying on the MachO MachineModuleInfo to live · 651f0192
  Chandler Carruth authored Nov 03, 2016
  651f0192
Nov 03, 2016
- [Cortex-M0] Atomic lowering · 962eaaea
  Weiming Zhao authored Nov 03, 2016
  962eaaea
- NFC - Test commit. · 946242b5
  Tony Jiang authored Nov 03, 2016
  946242b5
- AMDGPU/SI: Re add VIInstructions.td to unbreak bots · cc349831
  Tom Stellard authored Nov 03, 2016
  cc349831
- Remove a redundant condition found by PVS-Studio. · 5589aa60
  Chandler Carruth authored Nov 03, 2016
  5589aa60
- AMDGPU: Add VI i16 support · 2b3379cd
  Tom Stellard authored Nov 03, 2016
  2b3379cd
- Delete a dead store found by PVS-Studio. · 30e00299
  Chandler Carruth authored Nov 03, 2016
  30e00299
- [AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads. · f867a40b
  Alexander Timofeev authored Nov 03, 2016
  f867a40b
- Refactor creation of X86ISD::SETCC nodes to a helper function. NFC. · a455864f
  Zvi Rackover authored Nov 03, 2016
  a455864f
- Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently" · e7d97368
  James Molloy authored Nov 03, 2016
  e7d97368
- [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently · b60d8b19
  James Molloy authored Nov 03, 2016
  b60d8b19
- [AVX-512] Use 'vnot' instead of 'not' in patterns involving vXi1 vectors. · 7b9cc147
  Craig Topper authored Nov 03, 2016
  7b9cc147
- Expandload and Compressstore intrinsics · caaceef4
  Elena Demikhovsky authored Nov 03, 2016
  caaceef4
Nov 02, 2016
- [Hexagon] Remove registers coalesced in expand-condsets from live intervals · ead77016
  Krzysztof Parzyszek authored Nov 02, 2016
  ead77016
- AMDGPU: Allow additional implicit operands on MOVRELS instructions · 368972c3
  Nicolai Haehnle authored Nov 02, 2016
  368972c3
- Fix Clang-tidy readability-redundant-string-cstr warnings · 06ac79c2
  Malcolm Parsons authored Nov 02, 2016
  06ac79c2
- [ARM][MC] Cleanup ARM Target Assembly Parser · 0a392a8e
  Nirav Dave authored Nov 02, 2016
  0a392a8e
- [mips] Always run the MipsOptimizePICCall pass. · e3bb72ea
  Vasileios Kalintiris authored Nov 02, 2016
  e3bb72ea