llvm-svn: 74385

llvm-svn: 74384

llvm-svn: 74382

llvm-svn: 74368

llvm-svn: 74357

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

llvm-svn: 74322

llvm-svn: 74321

llvm-svn: 74293

Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288

llvm-svn: 74277

llvm-svn: 74255

llvm-svn: 74241

llvm-svn: 74239

llvm-svn: 74237

llvm-svn: 74236

llvm-svn: 74228

llvm-svn: 74223

llvm-svn: 74219

llvm-svn: 74212

llvm-svn: 74200

llvm-svn: 74185

llvm-svn: 74176

identify Thumb2.

llvm-svn: 74164

llvm-svn: 74161

Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.

llvm-svn: 74158

llvm-svn: 74156

llvm-svn: 74152

No need to code gen MDNodes

llvm-svn: 74150

llvm-svn: 74141

llvm-svn: 74138

llvm-svn: 74097

a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.

llvm-svn: 74096

llvm-svn: 74046

llvm-svn: 74042

createSCEV. Also, recognize UndefValue in createSCEV.

Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.

llvm-svn: 74041

C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.

llvm-svn: 74026

llvm-svn: 73990

llvm-svn: 73987