Use CodeGenTarget::getInstNamespace in one place and fix it.

llvm-svn: 98915

llvm-svn: 98914

llvm-svn: 98912

to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910

llvm-svn: 98908

llvm-svn: 98906

llvm-svn: 98904

llvm-svn: 98900

like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))

llvm-svn: 98897

llvm-svn: 98879

shouldn't change this.

llvm-svn: 98872

llvm-svn: 98871

llvm-svn: 98870

instruction.  Instructions must use 'ins' and 'outs' now.

llvm-svn: 98868

Add checking that the input/output operand list in spelled right.

llvm-svn: 98865

llvm-svn: 98859

to allow custom post-processing of matched instructions.

llvm-svn: 98857

llvm-svn: 98820

under valgrind:

==19577== Invalid free() / delete / delete[]
==19577==    at 0x4C9C866: free (vg_replace_malloc.c:325)
==19577==    by 0x5121104: ??? (in /lib/libc-2.10.2.so)
==19577==    by 0x4C97412: _vgnU_freeres (vg_preloaded.c:62)
==19577==    by 0x5041486: __run_exit_handlers (exit.c:93)
==19577==    by 0x50414FE: exit (exit.c:100)
==19577==    by 0x5028B5C: (below main) (libc-start.c:254)
==19577==  Address 0xffffffff is not stack'd, malloc'd or (recently) free'd
==19577== 

Apparently this happens under certain versions of glibc, so valgrind provides
the --run-libc-freeres=no option to avoid calling freeres().  This may increase
the number of "still reachable" blocks valgrind reports, but we don't care
about those, while this error breaks the buildbots.

There are upstream bugs about this at
http://sourceware.org/bugzilla/show_bug.cgi?id=10610 and
http://bugs.kde.org/show_bug.cgi?id=167483, but they don't look likely to be
fixed.

llvm-svn: 98813

llvm-svn: 98770

non-unit tests.

llvm-svn: 98741

U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640

(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98637

llvm-svn: 98633

have enums for them.

llvm-svn: 98597

now enforces that input/output named values have hte same type.

llvm-svn: 98535

changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534

llvm-svn: 98468

llvm-svn: 98449

llvm-svn: 98334

eliminate this problem. This will hopefully let us make progress on Linux
bootstrapping.

llvm-svn: 98095

llvm-svn: 98074

some other way when it comes to be necessary.

llvm-svn: 97972

needs to be majorly refactored, but this spot bugfix allows
things like:

 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
                             (vector_shuffle (v4i32 node:$lhs), node:$rhs), [{
...

llvm-svn: 97952

llvm-svn: 97912

llvm-svn: 97911

Now it will factor things like this:

CheckType i32
  ...
CheckOpcode ISD::AND
  CheckType i64
  ...

into:

SwitchType:
  i32: ...
  i64:
    CheckOpcode ISD::AND
    ...

This shrinks hte table by a few bytes, nothing spectacular.

llvm-svn: 97908

for CheckValueTypeMatcher.  The isContradictory implementation
helps us factor better, shrinking x86 table from 79144 -> 78896
bytes.

llvm-svn: 97905

llvm-svn: 97796

As in 'llvmc -O2 -O2 test.c'.

llvm-svn: 97787